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d a t a sh eet preliminary speci?cation file under integrated circuits, ic17 1996 dec 11 integrated circuits P90CL301bfh (c100) low voltage 16-bit microcontroller
1996 dec 11 2 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) contents 1 features 2 description 2.1 compatibility between P90CL301afh and P90CL301bfh 3 ordering information 4 block diagram 5 pinning information 5.1 pinning 5.2 pin description 6 system control 6.1 memory organization 6.2 programmable chip-select 6.3 dynamic bus port sizing 6.4 system control register (syscon) 6.5 reset operation 6.6 clock generation 6.7 interrupt controller 6.8 power reduction modes 7 cpu functional description 7.1 general 7.2 programming model and data organization 7.3 processing states and exception processing 7.4 tracing 7.5 stack format 7.6 cpu interrupt processing 7.7 bus arbitration 8 ports 8.1 port p control register (pcon) 8.2 port sp 8.3 ports schematics 9 8051 peripheral bus 10 on-chip peripheral functions 10.1 peripheral interrupt control 11 timers 11.1 timer array 11.2 timebase 11.3 channel function 11.4 pin parallel functions for the timer 11.5 timer control registers 11.6 timer status register 11.7 watchdog timer 12 serial interfaces 12.1 uart interface 12.2 baud rate generator 12.3 uart queue 12.4 i 2 c-bus interface 12.5 serial control register (scon) 13 pulse width modulation outputs (pwm) 13.1 prescaler pwm register (pwmp) 13.2 pwm data registers (pwm0 and pwm1) 14 analog-to-digital converter (adc) 14.1 adc control register (adcon) 15 on-board test concept 15.1 once mode 15.2 test rom 16 on-chip ram 17 register mapping 18 limiting values 19 dc characteristics 20 adc characteristics 21 ac characteristics 22 8051 bus timing 23 timing diagrams 24 clock timing 25 pin states in various modes 26 instruction set and addressing modes 26.1 addressing modes 27 instruction timing 28 package outline 29 soldering 29.1 introduction 29.2 reflow soldering 29.3 wave soldering 29.4 repairing soldered joints 30 definitions 31 life support applications 32 purchase of philips i 2 c components
1996 dec 11 3 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 1 features fully 68000 software compatible static design with 32-bit internal structure power saving modes: power-down, standby and idle mode external clock input: 27 mhz at 2.7 v single supply voltage of 2.7 to 3.6 v; down to 1.8 v for ram retention 68000 compatible bus interface intel 8051 compatible bus interface 16 mbytes program/data address range 8 programmable chip-selects dynamic bus sizing, 16 or 8-bit memory bus port size 56 powerful instruction types: C 5 basic data types, and C 14 addressing modes 7 programmable interrupt inputs: C a non-maskable interrupt input (nmin) C 14 auto-vectored interrupts and 7 interrupt priority levels 24 port pins (multiplexed with other functions) 2 uart serial interfaces; an independent baud rate generator with two programmable outputs (uart0 and uart1) uart queue with maximum 256 bytes i 2 c-bus serial interface 100 kbaud 2 timer arrays including: C two 16-bit reference counters and 8-bit programmable prescalers C six 16-bit match/capture registers with equality comparators watchdog timer with 21-bit resolution two 8-bit pulse width modulation (pwm) outputs with 8-bit prescaler four 8-bit analog-to-digital converter (adc) inputs with power-down mode 512 bytes ram on-chip on-circuit emulation (once) mode and internal test-rom (256 bytes) for on-board testing 80-pin lqfp package temperature range - 40 to +85 c 0.5 micron cmos low voltage technology. 2 description the P90CL301bfh is a highly integrated low-voltage 16/32-bit microcontroller especially suitable for digital mobile systems such as gsm, dcs1900, is54/95 and other applications requiring low voltage, low power consumption and high computing power. it is fully software compatible with the 68000. the P90CL301bfh optimizes system cost by providing both standard as well as advanced peripheral functions on-chip. the P90CL301bfh has a full static design and special idle, standby and power-down modes which allow further reduction of the total system power consumption. an 80-pin lqfp package dramatically reduces system size requirements. 2.1 compatibility between P90CL301afh and P90CL301bfh for functional compatibility between P90CL301afh (sac1 process) and P90CL301bfh (c100 process), the following points should be considered when using the P90CL301bfh: wake-up ; to wake-up the processor from power-down mode via the activation of an external spn pin, it is necessary to enable the interrupt mode first by setting the corresponding bit in the spcon register. syscon register ; for the P90CL301afh bits 11 to 15 in the syscon register should not be set in order to keep additional functionality in the P90CL301bfh inactive. 3 ordering information type number package temperature range ( c) name description version P90CL301bfh lqfp80 plastic low pro?le quad ?at package; 80 leads; body 12 12 1.4 mm sot315-1 - 40 to +85
1996 dec 11 4 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 4 block diagram h andbook, full pagewidth cpu 68000 reset ram 512 bytes port test rom data bus d15 to d0 address bus a31 to a0 watchdog timer 2 16-bit timers 6 channels bus interface baud rate generator uart0 uart1 pwm i 2 c-bus interface system ctrl 8-bit adc uart queue a23 to a1 lds uds as r/w d15 to d0 cp0 to cp5 tx0 rx0 tx1 rx1 pwm0 pwm1 scl sda v dda v ssa v ref(a) adc0 to adc3 dtack bsize halt reset resetin clock xtal1 interrupts int0 to int6 nmin sp0 to sp7 p0 to p15 d15 to d0 a31 to a0 csbt/once cs0 to cs2 mgd780 cs3 to cs6 v ss2 v ss1 v dd3 v dd2 v dd1 fig.1 P90CL301bfh block diagram.
1996 dec 11 5 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 5 pinning information 5.1 pinning fig.2 pinning diagram of the P90CL301bfh (lqfp80). n dbook, full pagewidth P90CL301bfh mgd773 1 as d7 d6 d5 d4 d3 d2 d1 d0 xtal1 v dd3 v ss1 uds/a0/ad0 a1/ad1 a2/ad2 a3/ad3 a4/ad4 a5/ad5 a6/ad6 a7/ad7 p15/adc3 v dda bsize p11/sda p10/scl p9/pwm1 (cp1) p8/pwm0 (cp0) sp0/rx1/int0 sp1/tx1/int1 (clk0) v ss2 sp2/rx0/int2 (cp2) sp3/tx0/int3 (cp3) sp4/int4 (cp4) sp5/int5 (cp5) sp6/int6 (clk1) nmin/sp7 cs0/fc0 cs1/fc1 cs2/fc2 cs3/ale lds [ds] r/w / trom dtack d8/p0 d9/p1 d10/p2 d11/p3 d12/p4 d13/p5 d14/p6 d15/p7 v dd1 halt reset resetin v ssa p12/adc0 p13/adc1 p14/adc2 v ref(a) a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 v dd2 a19/pcs0 a20/pcs1 a21/pcs2 a22/pcs3 cs6/a23 csbt/once cs5/wr cs4/rd 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1996 dec 11 6 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 5.2 pin description table 1 pin description for the P90CL301bfh symbol (1) pin description as 1 address strobe d7 to d0 2 to 9 lower 8-bits of data bus v dd3 10 supply voltage; third pin xtal1 11 external clock input v ss1 12 ground; ?rst pin uds/a0/ad0 13 upper data strobe or lsb of address bus or lsb of 8051 address/data a1/ad1 to a7/ad7 14 to 20 lower 7-bits of the 68000 address bus or lower 7-bits of the 8051 bus a8 to a18 21 to 31 upper 11-bits of the 68000 address bus v dd2 32 supply voltage; second pin a19/ pcs0 to a22/ pcs3 33 to 36 upper 4-bits of the address bus or 8051 bus chip-select cs6/a23 37 chip-select 6 or address bit 23 csbt/ once 38 chip-select boot or once mode forced input cs5/ wr 39 chip-select 5 or 8051 bus write strobe cs4/ rd 40 chip-select 4 or 8051 bus read strobe cs3/ale 41 chip-select 3 or 8051 bus address latch cs2/fc2 to cs0/fc0 42 to 44 chip-select 2 to 0 or data bus function code 2 to 0 nmin/sp7 45 non-maskable interrupt or second port pin (bit 7) sp6/ int6 (clk1) 46 second port pin (bit 6) external interrupt input 6 (external clock of timer 1) sp5/ int5 (cp5) 47 second port pin (bit 5) or external interrupt input 5 (timer 1 capture input 5) sp4/ int4 (cp4) 48 second port pin (bit 4) or external interrupt input 4 (timer 1 capture input 4) sp3/tx0/ int3 (cp3) 49 second port pin (bit 3) or transmit data for uart0 or external interrupt input 3 (timer 1 capture input 3) sp2/rx0/ int2 (cp2) 50 second port pin (bit 2) or receive data for uart0 or external interrupt input 2 (timer 0 capture input 2) v ss2 51 ground; second pin sp1/tx1/ int1 (clk0) 52 second port pin (bit 1) or transmit data for uart1 or external interrupt input 1 (external clock of timer 0) sp0/rx1/ int0 53 second port pin (bit 0) or receive data for uart1 or external interrupt input 0 p8/pwm0 (cp0) 54 port pin (bit 8) or pwm0 output (timer 0 capture input 0) p9/pwm1 (cp1) 55 port pin (bit 9) or pwm1 output (timer 0 capture input 1) p10/scl 56 port pin (bit 10) or i 2 c-bus serial clock. p11/sda 57 port pin (bit 11) or i 2 c-bus serial data. bsize 58 data bus size; 8 or 16-bit wide v dda 59 adc supply voltage p15/adc3 60 port pin (bit 15) or adc input 3 v ref(a) 61 adc reference voltage p14/adc2 to p12/adc0 62 to 64 port pin (bit 14 to bit 12) or adc inputs 2 to 0 v ssa 65 adc ground resetin 66 external power-on-reset input
1996 dec 11 7 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) note 1. the following notation is used to describe the multiple pin de?nitions: a) function1/function2/function3: multiplexed functions on the same pin. during and after reset the function1 is selected. b) function1 (function2): function done in parallel. c) function1 [function2]: equivalent function. reset 67 reset (bidirectional) hal t 68 halt (bidirectional) v dd1 69 supply voltage; ?rst pin d15/p7 to d8/p0 70 to 77 upper 8-bits of data bus or 8-bit port 7 to port 0; the selected function after reset is de?ned by pin bsize dt ack 78 data transfer acknowledge r/ w / trom 79 read/write bus control or test-rom forced input lds [ ds] 80 lower data strobe [word data strobe] symbol (1) pin description
1996 dec 11 8 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 6 system control 6.1 memory organization the maximum external address space of the controller is 16 mbytes. it can be partitioned into five address spaces. these address spaces are designated as either user or supervisor space and as either program or data space or as interrupt acknowledge. for slow memories the cpu can be programmed to insert a number of wait states. this is done via the eight chip-select control registers cs0n to cs7n; further to be denoted as csnn, where n = 0 to 7. the number of inserted wait states can vary from 0 to 6, or wait states are inserted until the dtack is pulled low by the external address decoding circuitry. if dtack is asserted continuously, the P90CL301bfh will run without wait states using bus cycles of three or four clock periods depending on the state of the fbc bit in the syscon register. 6.1.1 m emory map the memory address space is divided as shown in table 2; short addressing space with a31 to a15 = 1. table 2 memory address space address (hex) description 0000 0000 to 00ff ffff external 16 mbytes memory 0100 0000 to 8000 ffff not used 8001 0000 to 8001 ffff off-chip 64 kbytes on 8051 bus 8002 0000 to ffff 7fff not used ffff 8000 to ffff 8aff internal registers ffff 8b00 to ffff 8fff not used ffff 9000 to ffff 91ff internal 512 bytes ram ffff 9200 to ffff bfff not used ffff c000 to ffff c0ff internal 256 bytes test-rom ffff c100 to ffff ffff not used 6.2 programmable chip-select in order to reduce the external components associated with memory interface, the P90CL301bfh provides 8 programmable chip-selects. a specific chip-select csbt provides default reset values to support a bootstrap operation. each chip-select can be programmed with: a base address (a23 to a19) a memory bank width of 512 kbytes, 1, 2, 4 or 8 mbytes memory size a number of wait states (0 to 6 states, or wait for dtack) to adapt the bus cycle to the memory cycle time. chip-selects can be synchronized with read, write, or both read and write, either address strobe or data strobe. they can also be programmed to address low byte, high byte or word. each chip-select is controlled by a control register csnn (n = 0 to 7). the control registers are described in table 3 to 7. the reset instruction does not affect the contents of the csnn registers. register cs7n corresponds to register csbt (address ffff 8a0eh). after reset csbt is programmed with a block size of 8 mbytes with: a19 to a23 at logic 0 m19 to m22 at logic 1 6 wait states read only mode. the other chip-selects are held high and will be activated after initialization of their control registers. when programmed in reduced access mode (read only, write only, low byte, high byte), the wait states are generated internally and if there is any access-violation when the bit wd in the syscon register is set to a logic 1 (time-out), the processor will execute a bus error after the time-out delay.
1996 dec 11 9 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 6.2.1 c hip s elect c ontrol r egisters (cs0n to cs7n) table 3 chip select control registers cs0n to cs7n (address ffff 8a00h to ffff 8a0ch) table 4 description of cs0n to cs7n bits 1514131211109876543210 m22 m21 m20 m19 rw1 rw0 md1 md0 a23 a22 a21 a20 a19 ws2 ws1 ws0 bit symbol description 15 to 12 m22 to m19 address mask for block size selection; see table 5. 11 to 10 rw1 to rw0 read/write bus control (r/ w); see table 6. 9 to 8 md1 to md0 mode selection; see table 7. 7 to 3 a23 to a19 decoded base address; this should be a multiple of the block size (other codes are reserved for test or reset state); after reset: a23 to a19 = 11111 except for csbt. 2 to 0 ws2 to ws0 wait states 0 to 6 (see table 8); 7 wait states for dt ack to be pulled low by the external address decoding circuitry. the default value after reset is 110b for csbt and 111b for the other chip-selects. table 5 address mask for block size selection table 6 read/write bits (r/ w) table 7 mode selection m22 m21 m20 m19 block size 0000512 kbytes 00011 mbyte 00112 mbytes 01114 mbytes 11118 mbytes; default value after a cpu reset rw1 rw0 function 0 0 read only with length of as 0 1 write only with length of ds 1 0 write only with length of as 1 1 read/write with length of as; default value after a cpu reset md1 md0 function 0 0 alternate function 0 1 low byte access only 1 0 high byte access only 1 1 word access; default value after a cpu reset table 8 wait states selection note 1. the default value after a cpu reset. ws2 ws1 ws0 wait states 000 0 001 1 010 2 011 3 100 4 101 5 110 6 (1)
1996 dec 11 10 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) table 9 number of clock periods per bus cycle number of clock periods per bus cycle, dependent on the programmed length of fbc (fast bus cycle bit in the syscon register) and csn (chip-select). wait states length of cs n = length of as length of cs n = length of ds fbc = 1 fbc = 0 fbc = 1 fbc = 0 read write r/w read write read write 03443444 14444545 25555656 36666767 47777878 58888989 6999910910 6.3 dynamic bus port sizing the memory bus size can be selected to be 16 or 8-bit wide depending on the ports width of external memories and peripherals. it is possible via the register bsreg to define for each chip-select the bus width to 16-bit or 8-bit used for the transfer of data to or from external memory. the 7-bit register bsreg defines the bus size associated with each chip-select function (except for csbt). the bus size of the chip-select boot csbt (cs7n) is hardware defined by the pin bsize.the state of the pin bsize is latched at the end of the reset sequence. when an address generated by the cpu is identified by a chip-select block as belonging to its address segment, the corresponding bit of the register bsreg is used to define the sequence of bus transfer in 16 or 8-bit mode. several chip-selects with different bus sizes should not address the same memory segment. for each case the number of bus cycles necessary to transfer a byte, word or long word is a function of the bus size. for example, a word read on a 8-bit bus will take 2 bus cycles and the high byte is read first. the 8-bit port uses the pins d7 to d0. see table 11 and 12 and also section 6.2 for more detailed information on the programmable chip-selects and the dynamic bus sizing. 6.3.1 b us s ize r egister (bsreg) table 10 bus size register (address ffff a811h) table 11 description of bsreg bits 76543210 - bs6 bs5 bs4 bs3 bs2 bs1 bs0 bit symbol description 7 - reserved. 6 to 0 bs6 to bs0 bus size for the data transfer with respect to the corresponding chip-select ( cs6 to cs0). if bsn = 0, then the bus size is in 16-bit mode; the default value after a cpu reset. if bsn = 1, then the bus size is in 8-bit mode. where n = 0 to 6.
1996 dec 11 11 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) table 12 bus size depending on bsize, csbtx and bsn (n = 0 to 6) notes 1. depending on bit bsn in register bsreg. 2. the default value after reset of bits bsn in register bsreg is logic 0 which corresponds to 16-bit mode for cs0 to cs6. in this case, it is recommended to set bsn to logic 1 in the boot routine. afterwards if csbtx is set to logic 1, bsn can be reset to logic 0 by software for further transfers in 16-bit mode. 6.4 system control register (syscon) the P90CL301bfh uses a system control register (syscon) for adjusting system parameters. table 13 system control register (address ffff 8000h) notes 1. the default values after a cpu reset: pclk1 = 1 and pclk0 = 1; all other syscon bits are a logic 0. 2. all bits are reset by the reset instruction, except the idl bit which is only reset by a cpu reset. pin bsize bit csbtx bus size of cs0 to cs6 (1) bus size of csbtx port pl available (p0 to p7) bsn = 0 bsn = 1 at boot after boot 0 0 16 bit 8 bit 16 16 no 0 1 16 bit 8 bit 16 8 yes 1 0 note 2 8 bit 8 8 yes 1 1 16 bit 8 bit 8 16 no 15 14 13 12 11 10 9 8 7 (1) 6 (1) 54 3 21 (2) 0 wdsc bpe csbtx stby pclk3 pclk2 pde gf pclk1 pclk0 im wd fbc pd idl doff
1996 dec 11 12 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) table 14 description of syscon bits bit symbol description 15 wdsc bus error watchdog short cycle . wdsc = 0 for normal mode; the bus error watchdog counts 2048 periods before activating the bus error sequence. wdsc = 1 for bus error watchdog short cycle; the watchdog counts 16 periods before activating the bus error sequence. 14 bpe bus pull-up enable . if bpe = 0, the address and data bus internal pull-ups are switched off. if bpe = 1, the address and data bus internal pull-ups are switched on. 13 csbtx invert bus size for chip select boot and mode of port p0 to p7 . csbtx = 0 for normal mode; bus size is de?ned by the pin bsize. if csbtx = 1, the chip select boot is de?ned by the inverted value of the pin bsize. the mode change should be executed from the internal ram or from a memory activated by any other chip select than csbt. for further details see also section 6.3. 12 stby cpu standby mode . stby = 0, for normal mode. stby = 1, for standby mode; only the cpu clock is switched off, the peripheral clocks are still running (see fig.4). 11, 7 and 6 pclk3, pclk1 and pclk0 prescaler for primary peripheral clock (fclk) and the uart clock in mode 0 . the cpu clock = clk; fclk = 1 divisor clk. see table 15 for the divisor values. 10 pclk2 prescaler for secondary peripheral clock fclk2 (derived from the primary peripheral clock fclk), used for the adc; the maximum value of the fclk2 clock is dependent on the supply voltage v dd ; see section 19. if pclk2 = 0, then fclk is divided by 2; if pclk2 = 1, then fclk is divided by 4. 9 pde if pde = 0, then bits a22 to a19 are in normal operation; if pde =1, then bits a22 to a19 are used as 8051 peripheral chip-select pcs3 to pcs0. 8gf general purpose ?ag bit ; reset to a logic 0 after cpu reset. 5 im for im = 0, level 7 is loaded into the status register during interrupt processing to prevent the cpu from being interrupted by another interrupt source. for im = 1, the current interrupt level is loaded into the status register allowing nested interrupts. 4 wd for wd = 0, the time-out for bus error detection is switched off. if the time-out is not used, the watchdog timer can be used to stop a non-acknowledged bus transfer. for wd = 1, the time-out for bus error detection is activated. if no dt ack has been sent by the addressed device after 128 16 internal clock cycles the on-chip bus error signal is activated. 3 fbc fbc = 0, normal bus cycle; fbc = 1, fast bus cycle. an external read bus cycle can take a minimum of 3 clock periods; the minimum write cycle is still 4 clock periods; in order to get this access time dt ack should be asserted on time. 2 pd pd = 0, for normal mode; pd = 1, for power-down mode (see section 6.8). 1 idl idl = 0, for normal mode; idl = 1, for idle mode (see section 6.8). 0 doff doff = 0, for normal mode. doff = 1, for delay counter off; if set at wake-up from power-down the delay counter waiting period is skipped.
1996 dec 11 13 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) table 15 selection of prescaler divisor values pclk3 pclk1 pclk0 divisor (d) divisor for uart in mode 0 000 2 6 001 3 6 010 4 6 0 1 1 5 (default value after a cpu reset) 6 101 6 12 110 8 12 1 1 1 10 12 6.5 reset operation the reset circuitry of the P90CL301bfh is connected to the pins reset, halt, resetin and to the internal watchdog timer. a schmitt trigger is used at the input pin for noise rejection. after power-on a cpu reset is accomplished by holding the reset pin and the halt pin low for at least 50 oscillator clocks after the oscillator has stabilized. for further information on the clock generation, see section 6.6. the cpu responds by reading the reset vectors; the long word at address 000000h is loaded into the supervisor stack and the long word data at address 000004h is loaded into the program counter pc. the interrupt level is set to 7 in the status register and execution starts at the pc location. by pulling the reset pin low and keeping halt high, only the peripherals are reset. when v dd is turned on and its rise time does not exceed 10 ms, an automatic reset can be performed by connecting the resetin pin to v dd via an external capacitor. the external capacitor is charged via an internal pull-down resistor. the reset pin can also be pulled low internally by a pull-down transistor activated by an overflow of the watchdog timer. when the cpu executes a reset instruction, the reset pin is pulled low. when the cpu is internally halted (at double bus fault), the halt pin is pulled low and only a cpu reset can restart the processor. the internal signal reset_as (reset asynchronous) resets the core and all registers. when an internal watchdog timer overflow occurs, an internal cpu reset is generated which resets all registers except the syscon, pcon, prl and prh registers and pulls the reset pin low during 12 clock cycles.
1996 dec 11 14 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) handbook, full pagewidth latch latch peripheral reset reset_as cpu-reset cpu halt clk clk watchdog reset instruction reset double bus fault watchdog reset reset halt resetin v dd external reset capacitor r stin mbg330 fig.3 reset circuitry.
1996 dec 11 15 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 6.6 clock generation an external clock can be used with the P90CL301bfh. the duty cycle of the external clock should be 50/50 5% over the full temperature and voltage range. for peripherals like watchdog timer, i 2 c-bus, pwm, timer and baud rate generator, a programmable prescaler generates a peripheral clock fclk. the prescaler is controlled by the system control register (syscon). the internal clock is divided by a factor 2, 3, 4, 5, 6, 8 or 10 (function of bits pclk0, pclk1 and pclk3; see table 15). for the adc a secondary peripheral clock fclk2 is derived from the peripheral clock by dividing it either by 4 or 2 (function of the bit pclk2; see table 14). fig.4 P90CL301bfh internal clock generation. handbook, full pagewidth syscon (idl) syscon (pclk0, 1) syscon (pclk3) syscon (pclk2) xtal1 1/512 clk fclk mode 0 clock fclk2 uart1 uart0 1/2 1/3 1/4 1/5 1/2 1 1/4 1/2 brg scon cpu bcon 1 1/4 adc timer 0/timer 1 prescaler i 2 c-bus interface s1con pwm0/pwm1 watchdog idle mode mgd781
1996 dec 11 16 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 6.7 interrupt controller an interrupt controller handles all internal and external interrupts. it delivers the interrupt with the highest priority level to the cpu. the following interrupt requests are generated by the on-chip peripherals: i 2 c-bus uarts: received data / transmitted data timers: two flags for the timers t0 and t1 adc: analog-to-digital conversion completed. the external interrupt requests are generated with the pins nmin and the seven external interrupts int0 to int6. 6.7.1 i nterrupt arbitration the interrupt priority levels are programmable with a value between 0 and 7. level 7 has the highest priority, level 0 disables the corresponding interrupt source. in case of interrupt requests of equal priority level at the same time a hardware priority mechanism gives priority order as shown in table 16. the execution of interrupt routines can be interrupted by another interrupt request of a higher priority level. in 68070 mode (syscon bit im = 1) when an interrupt is serviced by the cpu, the corresponding level is loaded into the status register. this prevents the current interrupt from getting interrupted by any other interrupt request on the same or a lower priority level. if im is reset, priority level 7 will always be loaded into the status register and so the current interrupt cannot be interrupted by an interrupt request of a level less than 7. each on-chip peripheral unit including the eight interrupt lines generate only auto-vectored interrupts. no acknowledge is necessary. for external interrupts the vectors 25 to 31 are used, for on-chip peripheral circuits a second table of 7 vectors are used (57 to 63); see section 7.3.2. table 16 priority order 6.7.2 e xternal latched interrupts nmin and int0 to int6 are 8 external interrupt inputs. these pins are connected to the interrupt function only when the corresponding bit in the spcon control register is set (see section 8.2; table 29). seven interrupt inputs int0 to int6 are edge sensitive on high-to-low transition and their priority levels are programmable. the interrupt nmin is non-maskable (except if it is programmed as a port) and is also edge sensitive on high-to-low transition. the priority level of nmin is fixed to 7. the external interrupts are controlled by the registers lir0 to lir3; see tables 17 and 18. signal priority order nmin highest int6 int5 int4 int3 int2 int1 int0 i 2 c-bus adc uart1 receiver uart1 transmitter uart0 receiver uart0 transmitter timer 1 timer 0 lowest 6.7.2.1 latched interrupt registers (lir0 to lir3) table 17 latched interrupt registers address register 7 6 5 43210 fff 8101h lir0 pir1 ipl1.2 ipl1.1 ipl1.0 pir0 ipl0.2 ipl0.1 ipl0.0 fff 8103h lir1 pir3 ipl3.2 ipl3.1 ipl3.0 pir2 ipl2.2 ipl2.1 ipl2.0 fff 8105h lir2 pir5 ipl5.2 ipl5.1 ipl5.0 pir4 ipl4.2 ipl4.1 ipl4.0 fff 8107h lir3 pir7 1 1 1 pir6 ipl6.2 ipl6.1 ipl6.0
1996 dec 11 17 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) table 18 description of lir0 to lir3 bits 6.7.2.2 pending interrupt flag register (pifr) an additional register pifr contains copies of the pir flags. the pif flags are set at the same time as the pir flags when an interrupt is activated, but these flags are not reset automatically during the interrupt acknowledge cycle. they can only be cleared by software and keep a trace of the interrupt event. the detection of an external interrupt is indicated by the corresponding pif-bit being set to a logic 1. table 19 pending interrupt flag register (address ffff 810f) bit symbol description 7 and 3 pirn pending interrupt request . n = 0 to 7; int7 corresponds to the interrupt nmin; pirn = 1, pending interrupt request for pin intn. pirn = 0 (default value after a cpu reset), no pending interrupt. when a valid interrupt request has been detected this bit is set. it is automatically reset by the interrupt acknowledge cycle from the cpu. it can be reset by software by writing a logic 0, however writing a logic 1 has no effect on the ?ag. to reset only one ?ag, a logic 0 should be written to the bit address and a logic 1 to the other interrupt requests. the use of bclr instruction should be avoided (pir7 is cleared when the pin nmin is set high) 6to4 iplm.2 to iplm.0 interrupt priority level of pins int0 to int6 (fixed to 111b for nmin in lir3); m=0to6. 2to0 76543210 pif7 pif6 pif5 pif4 pif3 pif2 pif1 pif0 6.7.3 n ote on simultaneous interrupts if an internal interrupt is immediately followed by an external interrupt (i.e. both interrupts occurring within 12 clock cycles) and both these interrupts have the same interrupt level, then the cpu might hang up during the acknowledge cycle of the internal interrupt. in the interrupt controller a flag win is set for each interrupt as soon as the interrupt is activated and will be reset when an interrupt of higher priority occurs or during the acknowledge cycle. the win flag is used to determine which pir flag should be reset. a conflict occurs if within the interval starting at the cpu sampling of the first internal interrupt and ending at the acknowledge cycle, a second external interrupt resets the win flag of the first interrupt (external interrupts have higher priority than internal). when the cpu acknowledges the first internal interrupt the auto-vector acknowledge signal cannot be asserted as its win flag was reset, and the cpu hangs up. this situation can be solved by using the bus time-out counter controlled by the system control register (syscon) with the bits wd and wdsc set. in the case of hang-up an internal bus error condition will be asserted after 16 clocks and the cpu will execute the exception spurious interrupt at vector 60h. in the exception service routine the interrupt flags pir should be polled to detect which interrupts caused the conflict, the corresponding pir flags should be cleared by software and a call to the interrupt routines executed.
1996 dec 11 18 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 6.8 power reduction modes the P90CL301bfh supports three power reduction modes. a power-down mode where the clock is frozen, a standby mode where only the cpu is stopped, and an idle mode where the external clock is divided by 512 (see fig.4). 6.8.1 p ower - down mode the power-down operation freezes the oscillator. it can only be activated by setting the pd bit in the syscon register and thereafter execute the stop instruction. the instruction flow to enter the power-down mode is: bset #pd, syscon stop #$2700. in this state all the register contents are preserved. the cpu remains in this state until an internal reset occurs or a low level is present on any of the external interrupt pins int0 to int6 or nmin. if the wake-up is done via an external interrupt, the processor will first execute an external interrupt of level 7. if the ipl level in the lir register is set to 7, a second interrupt of level 7 will be executed. it is preferable to set the ipl to 0. in power-down mode v dd may be reduced to minimize power consumption. however, the supply voltage must not be reduced until power-down mode is active, and must be restored before a external reset or an interrupt is activated. in case of an external reset, the pin should be held active until the external oscillator has restarted and stabilized. in case of an external interrupt wake-up, any intn or nmin pin should go low and the corresponding bit esn (n = 0 to 7) in register spcon should be set. if the doff bit in the syscon is not set, an internal delay counter ensures that the internal clock is not active before 1536 clock cycles. after that time the oscillator is stable and normal exception processing can be executed. the pd bit is cleared automatically during the wake-up. in order to have a fast start-up the doff bit should be set, switching off the delay counter and enabling the immediate clocking and restart of the controller. for minimum power consumption during power-down mode, the address and data pins should be pulled high externally or bit bpe in register syscon should be set (i.e. internal pull-ups enabled). 6.8.2 s tandby mode when the stby bit in the syscon register is set, the cpu clock is stopped and the status of the processor is frozen, however, the clocks of all other on-chip peripherals are still running at the nominal frequency; these peripherals are: timers external and internal interrupts uarts and baud rate generator i 2 c-bus interface watchdog timer pwms adc. the cpu exits this mode when an internal or external interrupt is activated, and proceeds with the normal program execution. for minimum power consumption internal pull-ups on address and data buses can be switched on by setting the control bit bpe in the syscon register. the pull-ups should be switched off in normal mode if not needed. 6.8.3 i dle mode in the idle mode the crystal or external clock is divided by a factor 512. the current is reduced drastically but the controller continues to operate. this mode is entered by setting the bit idl in the syscon register. the next instruction will be executed at a slower speed. to return to normal mode the idl bit should be reset. it should be noted that all peripheral functions are also slowed down, and some cannot be used normally, for example uart, i 2 c-bus, adc and pwm. the power-down mode can also be entered from the idle mode. after a wake-up the controller restarts in idle mode.
1996 dec 11 19 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 7 cpu functional description 7.1 general the cpu of the P90CL301bfh is software compatible with the motorola mc68000, hence programs written for the mc68000 will run on the P90CL301bfh without modifications. however, for certain applications the following differences between processors should be noted: differences exist in the address/bus error exception processing since the P90CL301bfh can provide full error recovery. the timing is different for the P90CL301bfh due to a new internal architecture and technology. the instruction execution timing is different for the same reasons. 7.2 programming model and data organization the programming model is identical to that of the mc68000 (see fig.5), with seventeen 32-bit registers, a 32-bit program counter and a 16-bit status register. the eight data registers (d0 to d7) are used for byte, word and long-word operations. the address registers (a0 to a6) and the system stack pointer a7 can be used as software stack pointers and base address registers. in addition, these registers can be used for word and long-word address operations. all seventeen registers can be used as index registers. the P90CL301bfh supports 8, 16 and 32-bit integers as well as bcd data and 32-bit addresses. each data type is arranged in the memory as shown in fig.6. table 20 format of the status register and description of the bits; r = reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 t - s -- 12 11 10 --- xnzvc trace mode r supervisor r interrupt mask r extend negative zero over?ow carry
1996 dec 11 20 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) fig.5 programming model. n dbook, full pagewidth eight data registers program counter two stack pointers seven address registers a6 a0 31 16 15 8 7 0 do d1 d2 d3 d4 d5 d6 d7 user stack pointer supervisor stack pointer a7 31 16 15 0 a1 a2 a3 a4 a5 31 0 status register system byte user byte 15 8 7 0 mcd504
1996 dec 11 21 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) fig.6 memory data organization. (f) bcd data (2 bcd digits = 1 byte). (d) long-word data (32 bits). msb high order low order lsb 1514131211109876543210 bit high order low order high order low order (c) word data (16 bits). msb word 0 word 1 lsb 1514131211109876543210 bit word 2 (b) integer data (1 byte = 8 bits). msb byte 0 byte 2 lsb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit byte 1 byte 3 bcd 0 bcd 1 bcd 4 bcd 5 bcd 2 bcd 3 bcd 6 bcd 7 msb lsb 1514131211109876543210 bit mcd505 (e) addresses (1 address =32 bits). msb high order low order lsb 1514131211109876543210 bit high order low order high order low order (a) bit data (1 byte = 8 bits). 2 7 6543 1 0 bit long word 0 long word 1 long word 2 address 0 address 1 address 2
1996 dec 11 22 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 7.3 processing states and exception processing the P90CL301bfh operates with a maximum internal clock frequency of 27 mhz down to static operation. each clock cycle is divided into 2 states. a non-access machine cycle has 3 clock cycles or 6 states (s0 to s5). a minimum bus cycle normally consists of 3 clock cycles (6 states). when dtack is not asserted, indicating that data transfer has not yet been terminated, wait states (ws) are inserted in multiples of 2. the cpu is always in one of the four processing states: normal exception halt stopped. the normal processing state is associated with instruction execution; the memory references fetch instructions or load/save results. a special case of the normal state is the stopped state which is entered by the processor when a stop instruction is executed. in this state the cpu does not make any further memory references. the exception state is associated with interrupts, trap instruction, tracing and other exceptional conditions. the exception may be generated internally by an instruction or by any unusual condition arising during the execution of an instruction. externally, exception processing can be forced by an interrupt or by reset. the halted processing state is an indication of a catastrophic hardware failure. for example, if during exception processing of a bus error another bus error occurs, the cpu assumes that the system is unusable and halts. only an external reset can restart a halted processor. note that a cpu in the stopped state is not in the halted state or vice versa. the supervisor can work in the user or supervisor state determined by the state of bit s in the status register. accesses to the on-chip peripherals are achieved in the supervisor state. all exception processing is performed in the supervisor state once the current contents of the status register has been saved. then the exception vector number is determined and copies of the status register, the program counter and the format/vector number are saved on the supervisor stack using the supervisor stack pointer (ssp). finally the contents of the exception vector location is fetched and loaded into the program counter (pc). 7.3.1 r eference classification when the processor makes a reference, it classifies the kind of reference being made, using the encoding of the three function code internal lines. this allows external translation of addresses, control of access, and differentiation of special processor states, such as interrupt acknowledge. table 21 shows the classification of references. table 21 reference classi?cation 7.3.2 e xception vectors exception vectors are memory locations from where the cpu fetches the address of a routine that will handle that exception. all exception vectors are 2 words long, except for the reset vector which consists of 4 words, containing the pc and the ssp. all exception vectors are in the supervisor data space. a vector number is an 8-bit number which, multiplied by 4, gives the address of an exception vector. vector numbers are generated internally. the memory map for the exception vectors is shown in the table 22. function code reference class fc2 fc1 fc0 0 0 0 unassigned 0 0 1 user data 0 1 0 user program 0 1 1 unassigned 1 0 0 unassigned 1 0 1 supervisor data 1 1 0 supervisor program 1 1 1 interrupt acknowledge
1996 dec 11 23 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) table 22 exception vector assignment note 1. vectors 12, 13, 16 to 23 and 48 to 56 are reserved for future enhancements. vector no. decimal hex assignment 0 0 000 reset: initial ssp - 4 004 reset: initial pc 2 8 008 bus error 3 12 00c address error 4 16 010 illegal instruction 5 20 014 zero divide 6 24 018 chk instruction 7 28 01c trapv instruction 8 32 020 privilege violation 9 36 024 trace 10 40 028 line 1010 emulator 11 44 02c line 1111 emulator 12 (1) 48 030 unassigned, reserved 13 (1) 52 034 unassigned, reserved 14 56 038 format error 15 60 03c uninitialized interrupt vector 16 to 23 (1) 64 to 95 040 to 05c unassigned, reserved 24 96 060 spurious interrupt 25 100 064 level 1 external interrupt auto-vector 26 104 068 level 2 external interrupt auto-vector 27 108 06c level 3 external interrupt auto-vector 28 112 070 level 4 external interrupt auto-vector 29 116 074 level 5 external interrupt auto-vector 30 120 078 level 6 external interrupt auto-vector 31 124 07c level 7 external interrupt auto-vector 32 to 47 128 to 191 080 to 0bf trap instruction vectors 48 to 56 (1) 192 to 227 0c0 to 0e3 reserved 57 228 0e4 level 1 on-chip interrupt auto-vector 58 232 0e8 level 2 on-chip interrupt auto-vector 59 236 0ec level 3 on-chip interrupt auto-vector 60 240 0f0 level 4 on-chip interrupt auto-vector 61 244 0f4 level 5 on-chip interrupt auto-vector 62 248 0f8 level 6 on-chip interrupt auto-vector 63 252 0fc level 7 on-chip interrupt auto-vector 64 to 255 256 to 1023 100 to 3ff reserved
1996 dec 11 24 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 7.3.3 i nstruction traps traps are exceptions caused by instructions arising from cpu recognition of abnormal conditions during instruction execution or from instructions whose normal behaviour is to cause traps. some instructions are used specifically to generate traps. the trap instruction always forces an exception and is useful for implementing system calls for user programs. the trapv and chk instructions force an exception if the user program detects a run-time error, possibly an arithmetic overflow or a subscript out of bounds. the signed divide (divs) and unsigned divide (divu) instructions will force an exception if a divide-by-zero operation is attempted. 7.3.4 i llegal and unimplemented instructions illegal instruction is the term used to refer to any word that is not the first word of a legal instruction. during execution, if such an instruction is fetched an illegal exception occurs. words with bits 15 to 12 equal to 1010 or 1111 are defined as unimplemented instructions and separate exception vectors are allocated to these patterns for efficient emulation. this facility means the operating system can detect program errors, or can emulate unimplemented instructions in software. 7.3.5 p rivilege violations to provide system security, various instructions are privileged and any attempt to execute one of the privileged instruction while the cpu is in the user state provokes an exception. the privileged instructions are: stop reset rte move to sr and (word) immediate to sr eor (word) immediate to sr or (word) immediate to sr move to usp. 7.4 tracing the cpu includes a facility to trace instructions one by one to assist in program development. in the trace state, after each instruction is executed, an exception is forced so that the debugging program can monitor execution of the program under test. the trace facility uses the t-bit in the supervisor part of the status register. if the t-bit is cleared, tracing is disabled and instructions are executed normally. if the t-bit is set at the beginning of the execution of an instruction, a trace exception will be generated once the instruction has been executed. if the instruction is not executed, either because of an interrupt, or because the instruction is illegal or privileged, the trace exception does also not occur if the instruction is aborted by a reset, bus error, or address error exception. if the instruction is executed, and an interrupt is pending, the trace exception is processed before the interrupt. if the execution of an instruction forces an exception, the forced exception is processed before the trace exception. as an extreme illustration of the above rules, consider the arrival of an interrupt during the execution of a trap instruction, while tracing is enabled. first the trap exception is processed, followed by the trace exception, and finally the interrupt handling routine. 7.5 stack format the stack format for exception processing is similar to the mc68010 although the instruction stored is not the same, due to the different architecture. to handle this format the P90CL301bfh differs from the mc68000 in that: the stack format is changed. the minimum number of words put into or restored from stack is 4 (mc68010 compatible, not 3 as with the mc68000). the rte instruction decides (with the aid of the 4 format bits) whether or not more information has to be restored as follows: C the P90CL301bfh long format is used for bus errors and address error exceptions. C all other exceptions use the short format. if another format code, other than those listed above, is detected during the restored action, a format error occurs. if the user wants to finish the instruction in which the bus or address error occurred, the P90CL301bfh format must be used on rte. if no changes to the stack are required during exception processing, the stack format is transparent to the user.
1996 dec 11 25 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) table 23 description of the stack format symbol description sr status register. pch/pcl program counter high/low word. format indicating either a short stack (only the ?rst four words), or the long for bus and address error exceptions. base vector address the base vector address of the exception in the vector table; e.g. 8 for a bus error and 12 for an address error. ssw special status word. mm current move multiple mask. tpdh/tpdl in the event of faulty write cycle, the data can be found here. tpfh/tpfl the address used during the faulty bus cycle. dbinh/dbinl data that has been read prior to the faulty bus cycle can in some cases be found here. ir holds the present instruction executed. irc holds either the present instruction executed or the prefetched instruction. d book, full pagewidth short stack format format (4 bits) base vector address long stack format sr pch pcl ssw mm internal information internal information tpdh tpfl dbinh dbinl internal information ir irc tpfh tpdl sp mbg426 fig.7 stack format; see table 23.
1996 dec 11 26 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 7.6 cpu interrupt processing the general interrupt handling mechanism is described in section 6.7. an interrupt controller handles all interrupts, resolves the priority problem and passes the highest level interrupt to the cpu. the cpu interrupt handling follows the same basic rules as in the mc68000. however, some remarks must be made: interrupts with a priority level equal to or lower than the current priority level will not be accepted. during the acknowledge cycle of an interrupt, the ipl bits of the status register are set to the priority of the acknowledged interrupt or to 7. an exception occurs when bit im = 0 (syscon bit 5). in this case level 7 is loaded into the status register (see section 6.4; table 14). if the priority level of the pending interrupt is greater than the current processor priority then: the exception processing sequence is started a copy of the status register is saved the privilege level is set to supervisor state tracing is suppressed the priority level of the processor is set to that of the interrupt being acknowledged or to 7 depending on the im flag in the system control register. the processor then gets the vector number from the interrupting device, classifies it as an interrupt acknowledge and displays the interrupt level number being acknowledged on the internal address bus. as all P90CL301bfh interrupts are auto-vectored, the processor internally generates a vector number corresponding to the interrupt level number. the processor starts normal exception processing by saving the format word, program counter and status register on the supervisor stack. the value of the vector in the format word is an internally generated vector number multiplied by 4 (format is all zeros). the program counter value is the address of the instruction that would have been executed if the interrupt had not been present. then the interrupt vector contents are fetched and loaded into the program counter. the interrupt handling routine starts with normal instruction execution. 7.7 bus arbitration if the halt pin is held low with reset high the cpu will stop after completion of the current bus cycle. as long as halt is low, all control signals are inactive and all 3-state lines are placed in the high-impedance state. if the halt pin is held low during the transfer of a word in 8-bit mode, the cpu will continue the transfer of the two bytes before it halts.
1996 dec 11 27 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 8 ports for general purpose input/output operations the following ports can be used: 16-bit bidirectional port lines p15 to p0 composed of two 8-bit ports pl (p7 to p0) and ph (p15 to p8) 8-bit port lines sp7 to sp0. all port pins are multiplexed with other functions, but each one can be individually switched to the port function by setting the corresponding bit in the port p control register (pcon) for port pn and port sp control register (spcon) for port spn. the port p7 to p0 is multiplexed with the data bus d15 to d8 and is selected by the pin bsize. each port pin consists of a latch, an output driver with pull-ups and an input buffer. to use the port as input the port latch should be written with a logic 1. this means only a weak pull-up is on and can be overwritten by an external source logic 0. when outputting a logic 1, a strong pull-up is turned on only for 1 clock period, and then only the weak pull-up maintains the high level. in read mode, two different internal addresses correspond to the port latch or the port pin.the port values are read via register ppl and pph. after reset all ports are initialized as input, and the pins are connected to the port latch with exception for the pin nmin/sp7 which is connected to the interrupt block. 8.1 port p control register (pcon) the port pn is controlled via the port p control register (pcon). the register pcon is only reset by an external reset, and not by the reset instruction. the port latches are accessed through the registers prl and prh. table 24 port p control register (address ffff 8503h) table 25 description of pcon bits 8.1.1 p ort pl atches table 26 port p latch least signi?cant byte (prl; address ffff 8505h) table 27 port latches high most signi?cant byte (prh; address ffff 8509h) 76543210 e15 e14 e13 e12 e11 e10 e9 e8 bit symbol description 7 to 0 e15 to e8 if en = 0, then port pn is enabled; if en = 1, then the alternate function is enabled; n = 8 to 15. the default value after reset is logic 0. 76543210 p7 p6 p5 p4 p3 p2 p1 p0 76543210 p15 p14 p13 p12 p11 p10 p9 p8
1996 dec 11 28 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 8.2 port sp control register (spcon) the special ports spn (sp0 to sp7) consist of 8 i/o lines and are controlled via the two registers spcon and spr. the registers spcon and spr are reset by a peripheral reset. the port latch is accessed through the register spr. 8.2.1 p ort sp c ontrol r egister (spcon) table 28 port sp control register (address ffff 8109h) table 29 description of spcon bits 8.2.2 p ort sp latch (spr) table 30 port sp latch (ffff 810bh) 76543210 es7 es6 es5 es4 es3 es2 es1 es0 bit symbol description 7 to 0 es7 to es0 if esn = 0, then port spn is enabled; if esn = 1, then the alternate function is enabled; n = 0 to 7. the default value after reset is logic 0, except for es7 which is set at reset. 76543210 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 8.2.3 a lternative functions for ports p and sp table 31 alternative functions for p0 to p15 and sp0 to sp7 pins functions within brackets are parallel functions. port pin alternate function p0 d8 p1 d9 p2 d10 p3 d11 p4 d12 p5 d13 p6 d14 p7 d15 p8 pwm0 (cp0) p9 pwm1 (cp1) p10 scl p11 sda p12 adc0 p13 adc1 p14 adc2 p15 adc3 sp0 rx1/ int0 sp1 tx1/ int1 (clk0) sp2 rx0/ int2 (cp2) sp3 tx0/ int3 (cp3) sp4 int4 (cp4) sp5 int5 (cp5) sp6 int6 (clk1) sp7 nmin port pin alternate function
1996 dec 11 29 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) fig.8 port schematics (continued in fig.9). a. wp2 + wp4 port. b. an + wp2 (p15 to p12) port. handbook, full pagewidth delay p from port latch q n p p data input mgd784 i/o pin v dd handbook, full pagewidth delay p n n p p p enable virtual ground cia adc block data input mgd787 i/o pin v dd from port latch q
1996 dec 11 30 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) handbook, full pagewidth n data input mgd783 external pull-up pin fig.9 port schematics (continued from fig.8). handbook, halfpage n p data input mgd785 pin v dd handbook, halfpage n power down mgd786 pin v dd r vref a. open-drain port. b. 3-state port. c. aref input. 9 8051 peripheral bus the P90CL301bfh can also directly access the peripheral circuits which are compatible with the 8048/8051 bus. when the cpu accesses locations located in the 64 kbytes peripheral space, an address/data multiplexed access is generated using the ad0 to ad7 lines, the non-multiplexed a8 to a15 lines and the 8051 control bus (ale, rd, wr). in order to use these three signals the alternate mode of the cs5 to cs3 should be set. a 8051 bus access is performed by addressing a byte in the 8001 0000h to 8001 ffffh range. to reduce the number of interface circuits, the address lines a22 to a19 can be used as peripheral chip-select outputs pcs0 to pcs3. this is done by setting the pde bit (syscon) to a logic 1; pcs0 selects memory range 0 kbytes to 16 kbytes pcs1 selects memory range 16 kbytes to 32 kbytes pcs2 selects memory range 32 kbytes to 48 kbytes pcs3 selects memory range 48 kbytes to 64 kbytes. the timing of the peripheral bus is fixed and compatible with the 8051 peripheral circuits.
1996 dec 11 31 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 10 on-chip peripheral functions the P90CL301bfh integrates a number of peripheral functions connected to the internal bus: timers (t0 and t1) watchdog 2 uart interfaces with one uart queue controller using the internal ram as data buffers. i 2 c-bus interface pwm (pulse width modulation) adc (analog-to-digital converter). these functions are accessible as memory locations on a byte or word basis. the access is auto-acknowledged by on-chip logic. the on-chip peripheral functions can generate auto-vectored interrupts to the cpu using the second vector table (vectors 57 to 63). 10.1 peripheral interrupt control the timers t0 and t1, i 2 c-bus, uart and adc use a common set of peripheral interrupt control registers (picrn; n = 0 to 3). these registers are accessible from the cpu and contain the interrupt priority level flags ipl2 to ipl0 as well as the pending interrupt flags pir. pir is set when a valid interrupt request has been detected. it is automatically reset by the interrupt acknowledge cycle from the cpu. the pir flag can be reset by software. the interrupt priority level code 111b represents the interrupt with the highest priority. the code 000b inhibits the interrupt. 10.1.1 t imer i nterrupt r egister (picr0) on timer overflow or on channel capture/match the pending interrupt request flag pirtn is set. if the interrupt priority level is different from zero, the timer activates an interrupt to the cpu. table 32 timer interrupt register (address ffff 8701h) table 33 description of picr0 bits 7 6 5 4 3 2 1 0 pirt1 iplt1.2 iplt1.1 iplt1.0 pirt0 iplt0.2 iplt0.1 iplt0.0 bit symbol description 7 pirt1 pending interrupt for timer t1 6 to 4 iplt1.2 to iplt1.0 interrupt priority level for timer t1 3 pirt0 pending interrupt for timer t0 2 to 0 iplt0.2 to iplt0.0 interrupt priority level for timer t0
1996 dec 11 32 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 10.1.2 uart i nterrupt r egisters each uart can generate two interrupts in transmission and reception via the two registers picr1 and picr2. table 34 uart interrupt registers picr1 (address ffff 8703h) table 35 description of picr1 bits table 36 uart interrupt registers picr2 (address ffff 8705h) table 37 description of picr2 bits 10.1.3 i 2 c- bus and adc i nterrupt r egister (picr3) the i 2 c-bus and the adc respectively, can generate one interrupt. table 38 i 2 c-bus and adc interrupt register (address ffff 8707h) table 39 description of picr3 bits 76543210 pirr0 iplr0.2 iplr0.1 iplr0.0 pirt0 iplt0.2 iplt0.1 iplt0.0 bit symbol description 7 pirr0 pending interrupt for uart0 in reception 6 to 4 iplr0.2 to iplr0.0 interrupt priority level for uart0 in reception 3 pirt0 pending interrupt for uart0 in transmission 2 to 0 iplt0.2 to iplt0.0 interrupt priority level for uart0 in transmission 76543210 pirr1 iplr1.2 iplr1.2 iplr1.2 pirt1 iplt1.2 iplt1.1 iplt1.0 bit symbol description 7 pirr1 pending interrupt for uart1 in reception 6 to 4 iplr1.2 to iplr1.0 interrupt priority level for uart1 in reception 3 pirt1 pending interrupt for uart1 in transmission 2 to 0 iplt1.2 to iplt1.0 interrupt priority level for uart1 in transmission 7 6 5 4 3 2 1 0 piri ipli2 ipli1 ipli0 pira ipla2 ipla1 ipla0 bit symbol description 7 piri pending interrupt for i 2 c-bus 6 to 4 ipli2 to ipli0 interrupt priority level for i 2 c-bus 3 pira pending interrupt for adc 2 to 0 ipla2 to ipla0 interrupt priority level for adc
1996 dec 11 33 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 11 timers 11.1 timer array two identical 16-bit timer blocks are provided: timer 0 (t0) timer 1 (t1). each timer block consists of: a timebase three capture/compare channels a control register a status register. 11.2 timebase the timebase contains an 8-bit prescaler with a write only reload register, and a 16-bit counter register. this counter register can only be read by software. the prescaler is clocked either by the peripheral clock fclk or by an external clock enabled by the flag c/tn in the timer control register tncr (t0ct for timer t0 and t1cr for timer t1). on prescaler overflow the prescaler reload value is loaded into the prescaler, which starts incrementing. the 16-bit counter register is incremented at each prescaler overflow. when the counter reaches ffffh, the status flag tov is set and on the next clock the counter reload value is loaded into the counter. by resetting the control bit run in the timer control register the timebase is stopped, and by setting this bit, the prescaler and counter are reloaded and incremented on the next external or internal clock. 11.3 channel function each channel consists of a register and an equality comparator. for each of the three channels two modes can be selected: compare mode: sets the status flag cfn in tnsr when there is a match between the counter register and the channel register value. capture mode: stores the counter register value into the channel register and sets the status flag cfn when a transition occurs at the corresponding input pin cpn. in both modes, each channel can generate a global interrupt request if the corresponding enable bit in the control register tncr is set. 11.4 pin parallel functions for the timer in order to use the multiplexed pins for the timer, the other functions using these pins as output pins should be forced high via a weak pull-up, enabling an external source to drive them low. table 40 parallel functions pin setting parallel function sp1/tx1/ int1 if spcon.1 = 0, spr.1 = 1; else uart1 should not be used clk0 sp2/rx0/ int2 if spcon.2 = 0, spr.2 = 1; else uart0 should not be used cp2 sp3/tx0/ int3 if spcon.3 = 0, spr.3 = 1; else uart0 should not be used cp3 sp4/ int4 if spcon.4 = 0, spr.4 = 1 cp4 sp5/ int5 if spcon.5 = 0, spr.5 = 1 cp5 sp6/ int6 if spcon.6 = 0, spr.6 = 1 clk1 p8/pwm0 if pcon.0 = 0, pwm0 should output a logic 1 (write 00h to register pwm0) cp0 p9/pwm1 if pcon.1 = 0, pwm1 should output a logic 1 (write 00h to register pwm1) cp1
1996 dec 11 34 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) fig.10 timer block diagram t0 (identical with timer block t1, corresponding names indicated within brackets). handbook, full pagewidth 4 16 16 16 16 timer status register t0sr (t1sr) 4 4 16 16 16 16 8 16 channel register t0c2 (t1c5) edge detection cp2 (cp5) cp1 (cp4) cp0 (cp3) c2f (c5f) c1f (c4f) c0f (c3f) edge detection edge detection 16 channel register t0c1 (t1c4) compare unit 16 16 compare unit 16 channel register t0c0 (t1c3) counter register t0 (t1) prescaler prescaler reload register 16 16 16 counter reload register t0rr (t1rr) timer control register t0cr (t1cr) 16 8 compare unit pirt0 (pirt1) internal bus 0 1 fclk clk0 (clk1) cp0 (cp3) gate c/tn tov mbg332
1996 dec 11 35 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 11.5 timer control registers the timer 0 (t0) is controlled via timer 0 control registers (t0crh and t0crl), and timer 1 (t1) via timer 1 control registers (t1crh and t1crl); see fig.10 and tables 41 to 44. the default value after a cpu reset for all bits of t0crh; t1crh; t0crl and t1crl is a logic 0. table 41 timer control registers t0crh and t1crh table 42 timer control registers t0crl and t1crl table 43 description of t0crh; t1crh; t0crl and t1crl bits address register 15 14 13 12 11 10 9 8 ffff 8300h t0crh ecm2 c2m2 c2m1 c2m0 ecm1 c1m2 c1m1 c1m0 ffff 8310h t1crh address register 7 6 5 4 3 2 1 0 ffff 8301h t0crl ecm0 c0m2 c0m1 c0m0 etov gate c/tn run ffff 8311h t1crl bit symbol description 15, 11 and 7 ecm2 to ecm0 channel n interrupt enable (n = 0 to 2); ecmn = 0, the channel n interrupt is disabled; ecmn = 1, the channel n interrupt is enabled. 14 to 12 c2m2 to c2m0 channel mode ; see table 44. 10 to 8 c1m2 to c1m0 6 to 4 c0m2 to c0m0 3 etov timer overflow interrupt enable ; etov = 0, the timer overflow interrupt is disabled; etov = 1, the timer overflow interrupt is enabled. 2gate gated external clock ; gate = 0, disable gate function; gate = 1, the prescaler increments only if the cp0 pin is high for each rising edge transition of clk0 if c/tn = 1 or with fclk if c/tn = 0. 1 c/tn counter/timer mode; c/tn = 0, timer mode; the prescaler is incremented on the rising edge of the peripheral clock (fclk); c/tn = 1, counter mode; the prescaler increments on the rising edge of clk0 for timer 0 (clk1 for timer 1). 0 run timer run enable ; run = 0, timer prescaler stopped and registers value held; run = 1, when set the prescaler and counter are loaded and the prescaler is then incremented.
1996 dec 11 36 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) table 44 description of channel mode; n = 0 to 5; x = dont care 11.6 timer status registers four events can occur: a timer overflow or three channel matches/captures. these event flags are stored in the 4-bit timer 0 status register (t0sr for t0) and timer 1 status register (t1sr for t1). they can be cleared by software but cannot be set. by writing a logic 1 the flags stay unchanged. in order to clear a particular flag one has to write a logic 0 to the corresponding position and logic 1s to the others. one should avoid to use the instruction bclr, which can reset accidentally several flags. 11.6.1 t imer 0s tatus r egister (t0sr) table 45 timer 0 status register (address ffff 830dh) table 46 description of t0sr bits 11.6.2 t imer 1s tatus r egister (t1sr) table 47 timer 1 status register (address ffff 831dh) table 48 description of t1sr bits cnm2 cnm1 cnm0 description 0 0 0 channel n inhibited 0 0 1 channel n capture on low-to-high transition of pin cpn 0 1 0 channel n capture on high-to-low transition of pin cpn 0 1 1 channel n capture on any transitions of pin cpn 1 x x channel compare mode 76543210 ---- c2f c1f c0f tov bit symbol description 7to4 - reserved. 3 to 1 c2f to c0f channel n event flag (n = 2 to 0); cnf = 0, no event (default value after a cpu reset). cnf = 1, capture mode: a capture occurred. 0 tov timer overflow flag; tov = 0, no over?ow (default value after a cpu reset). tov = 1, timer over?ow occurred. 76543210 ---- c5f c4f c3f tov bit symbol description 7to4 - reserved. 3 to 1 c5f to c3f channel n event flag (n = 5 to 3); cnf = 0, no event (default value after a cpu reset). cnf = 1, capture mode: a capture occurred. 0 tov timer overflow flag; tov = 0, no over?ow (default value after a cpu reset). tov = 1, timer over?ow occurred.
1996 dec 11 37 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 11.7 watchdog timer the P90CL301bfh contains a watchdog timer consisting of a 13-bit prescaler and an 8-bit timer wdtim. the prescaler is incremented by the peripheral clock. the 8-bit timer is incremented every 8192 cycles of the peripheral clock fclk. if the fclk frequency is 2 mhz, the watchdog timer can operate in the range of 4.1 ms up to 1 s. the watchdog timer is disabled after reset. it can be enabled by writing any value to the wdcon register. the only way to disable a running watchdog timer is to reset the P90CL301bfh. when a timer overflow occurs the microcontroller will be reset (except registers syscon, pcon, prl and prh which will not be reset). to prevent an overflow of the watchdog timer, the user program must reload the watchdog register within a period shorter than the programmed timer interval. this timer interval is determined by the 8-bit timer value written to the register wdtim. for fclk in mhz, the watchdog period is: the watchdog timer is controlled by the register wdcon. a value of a5h in wdcon clears both the prescaler and timer wdtim. after reset, wdcon contains a5h. every value other than a5h in wdcon enables the watchdog timer. since the bit 0 of the wdcon input is tied to a logic 0 by hardware during write operations on wdcon, the reset value a5h can not be programmed again and can only be restored by a reset. timer wdtim can be written only if wdcon has previously been loaded with 5ah, otherwise wdtim and the prescaler are not affected. a successful write operation to wdtim also clears the prescaler and clears wdcon. only the values a5h or 5ah are stored, all other values are stored with a dummy value 00h. 256 wdtim C () 8192 fclk -------------- - m s fig.11 watchdog timer block diagram. handbook, full pagewidth mbg325 internal bus prescaler 13-bit counter register 8-bit wdcon register wdtim 8-bit reload register fclk fclk/8192 enable overflow internal reset
1996 dec 11 38 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 12 serial interfaces 12.1 uart interface the uart can operate in 4 modes. the baud rate for receive and transmit can be generated internally or by the baud rate generator. the uart is full duplex, meaning it can receive and transmit simultaneously. the receive and transmit registers are both accessed as a unique register sbuf. writing to sbuf loads the transmit register, and reading from sbuf accesses a physically separate receive register. 12.1.1 uart operating modes the serial port can operate in one of the four modes: mode 0 serial data enters and exits through rxd. txd pin delivers the synchronous shift clock. 8 bits are transmitted/received (lsb first). when the bit pclk3 in the syscon register is reset, the baud rate is equal to 1 6 clk. when the bit pclk3 in register syscon is set, the baud rate is equal to 1 12 clk. the uart baud rate should not exceeds 4.5 mbaud. mode 1 10 bits are transmitted (through txd) or received (through rxd): a start bit at logic 0, 8 data bits (lsb first) and a stop bit at logic 1. on receive the stop bit goes into rb8 in the register scon. the baud rate is given by the baud rate generator output bgclk0 for the uart0 and bgclk1 for the uart1. mode 2 11 bits are transmitted (through txd) or received (through rxd): a start bit at logic 0, 8 data bits (lsb first) a programmable 9 th data bit, and a stop bit at logic 1. on transmit the 9 th bit is taken from the bit tb8 from the scon register. on receive the 9 th bit goes into rb8 of scon, while the stop bit is ignored. the baud rate is equal to 1 6 clk. the uart clock should not exceed 4.5 mbaud. mode 3 same as mode 2 except for the baud rate, which is given by the baud rate generator output bgclk0 for the uart0 and bgclk1 for the uart1. in all four modes, transmission is initiated by any instruction loading sbuf. in mode 0, reception is initiated by the condition ri = 0 and ren = 1. in the remaining modes reception is initiated by the incoming start bit if ren = 1.
1996 dec 11 39 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 12.1.2 uart c ontrol r egisters scon0 and scon1 the registers scon0 and scon1 control uart0 and uart1 modes respectively, and contain the interrupt flags. table 49 uart control registers scon0 and scon1 table 50 description of register scon0 and scon1 bits table 51 mode de?ned by bits sm0 and sm1 address register 7 6 5 4 3 2 1 0 ffff 8603h scon0 sm0 sm1 sm2 ren tb8 rb8 ti ri ffff 8607h scon1 bit symbol description 7 to 6 sm0 to sm1 mode bits; see table 51. 5 sm2 multiprocessor ; enable the multiprocessor communication feature in modes 2 and 3. if sm2 is set the ri will not be activated if the received 9 th data bit rb8 = 0. in mode 1, if sm2 is set the ri will not be activated if a valid stop bit is not received. in mode 0, sm2 should be a logic 0. 4 ren receive enable ; enables serial reception; set and cleared by software. 3 tb8 transmit extra bit ; 9 th data bit that will be transmitted in modes 2 and 3; set and cleared by software. 2 rb8 receive extra bit ; in modes 2 and 3, rb8 is the 9 th bit received. in mode 1, if sm2 = 0, rb8 is the stop bit which is received. 1ti transmit interrupt ; it is set by hardware at the end of the 8 th bit time in mode 0, or halfway through the stop bit in the other modes (except: see bit sm2). ti must be cleared by software (cannot be set by software). by writing a logic 1 the flags stay unchanged. in order to clear a particular flag one has to write a logic 0 to the corresponding position and a logic 1 to the others. one should avoid to use the instruction bclr, which can reset accidentally several flags. 0ri receive interrupt ; set by hardware at the end of the 8 th bit time in mode 0, or halfway through the stop bit in the other modes (except: see sm2). ri must be cleared by software (cannot be set by software). by writing a logic 1 the flags stay unchanged. in order to clear a particular flag one has to write a logic 0 to the corresponding position and a logic 1 to the others. one should avoid to use the instruction bclr, which can reset accidentally several flags. sm0 sm1 mode description 0 0 0 shift register; 1 6 clk 0 1 1 8-bit uart; bgclk0 and bgclk1 1 0 2 9-bit uart; 1 16 clk 1 1 3 9-bit uart; bgclk0 and bgclk1
1996 dec 11 40 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 12.2 baud rate generator a dedicated baud rate generator is directly connected to the uart0. for the uart1 this clock can be divided by 1 or 4 as a function of the bit bdiv in the bcon control register. the baud rate generator consists of a 16-bit timer, two 8-bit registers bregl (least significant byte) and bregh (most significant byte) to store the 16-bit reload value, and a control register bcon. when an overflow occurs the timer is reloaded with the contents of the registers bregh, bregl. the timer is clocked by the peripheral clock. the baud rates for uart0 and uart1 in mode 1 and 3 are determined by the timer overflow rate as follows (fclk is in hz): bgclk0 fclk 16x 65536 breg C () () --------------------------------------------------------------- - = bgclk1 fclk 16 65536 breg C () x4 bdiv ? ?? ----------------------------------------------------------------------------------- - = 12.2.1 uart b aud r ate c ontrol r egister (bcon) the default value after a cpu reset for all bits of bcon is a logic 0. table 52 uart baud rate control register (address ffff 860fh) table 53 description of bcon bits 7 6 5 4 3 2 1 0 ------ bst bdiv bit symbol description 7to2 - reserved. 1 bst bst = 0, stop timer; bst = 1, start timer increment after loading of timer register with the reload register value. 0 bdiv bdiv = 0, uart1 baud rate not divided; bdiv = 1, uart1 baud rate divided by 4. 12.3 uart queue the uart queue performs the sending and receiving of a frame of bytes of variable length through the uart without the support of the cpu. only the uart0 has a frame buffer located at the lower 256 bytes section of the internal ram. a controller ensures the sequencing of the transfers between the ram and the uart and generates interrupts to the cpu. this uart queue can be used for transmission and reception simultaneously or for only one of the two modes. the ram can be accessed by the cpu any time. the queue controller accesses the ram either in read mode for the transmission or in write mode for the reception. when the queue controller accesses the ram, the cpu waits for the end of the access cycle (maximum 4 clk clocks). the ram space can be partitioned in one or several buffers for transmission or reception or for normal data storage. the maximum size of a buffer is limited to 256 bytes. in addition to these buffers the queue consists of a set of control and data registers:
1996 dec 11 41 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) table 54 function of uart queue registers notes 1. uqrc and uqtc can be accessed together as a word or as two bytes. 2. for each byte transmitted the uqta is incremented, the uqts is decremented. 3. for each byte received the uqra is incremented, the uqrs is decremented.the cpu can read this register on the fly, but in this case the accuracy is not guaranteed so it is recommended to halt the queue and read the values. name function description size uqrc (1) reception control register reception control and status ?ags. byte uqtc (1) transmission control register and interrupt flags. transmission control and status ?ags and interrupt ?ags. byte uqta (2) transmit buffer address register start address of transmission buffer from 00h to ffh, corresponds to cpu address from ffff 9000h to ffff 90ffh. byte uqts (2) transmit buffer size register size of the transmission buffer. limited to 256 bytes. byte uqra (3) reception buffer address register start address of reception buffer from 00h to ffh, corresponds to cpu address from ffff 9000h to ffff 90ffh. byte uqrs (3) reception buffer size register size of the reception buffer. limited to 256 bytes. byte uqrm reception match register the received characters are compared with the value contained in this register and an interrupt is generated when they are equal. byte fig.12 uart queue block diagram. handbook, full pagewidth uqts uqrs decr zero mgd782 data bus address bus ten uqrc uqtc uart queue control uqrm scon0 ti tx data bus rx rif tif ri mux mux mux tx sbuf0 rx sbuf0 ram 256 bytes incr = uqra uqta
1996 dec 11 42 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 12.3.1 r eception c ontrol r egister (uqrc) in order to keep the bit unchanged when writing to the control register, it is recommended to write a logic 1 when it can only be reset, and to write a logic 0 when it can only be set. after peripheral reset all bits are set to a logic 0. table 55 reception control register (address ffff 8b00h) notes 1. cpu. r: the cpu can reset this bit. s: the cpu can set this bit. 2. queue. r: the queue controller can reset this bit. s: the queue controller can set this bit. table 56 description of uqrc bits action of bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ren rme rie roe rof rar rhlt rstf cpu (1) s/r s/r s/r s/r r s/r s/r s queue (2) ---- s -- r bit symbol description 7 ren receive queue enable . this bit enables the queue controller. it connects the reception data buffer sbuf0 to the queue controller. it should be set before activating the rstf bit. when it is reset sbuf0 can be accessed directly by the cpu. ren = 0 means receive queue disable. received byte can be read directly from sbuf0. ren = 1 means receive queue enable: the transfers from the sbuf0 to the ram can be activated by setting the bit rstf. 6 rme reception match enable . if it is set each received byte is compared with the content of the uart queue receive match register (uqrm) and if their value match the receive interrupt ?ag rif is set. rme = 0 means match function disabled. rme = 1 means match function enabled. 5 rie reception interrupt enable . when this bit is set, each time a byte is received the receive interrupt ?ag rif is set. if it is not set, an interrupt is only generated at the end of the frame. rie = 0 means no interrupt after the reception of each byte, only at the end of the frame. rie = 1 means interrupt after the reception of each byte. 4 roe reception over?ow enable . when this bit is set, the rstf bit is not reset when the reception buffer size reached 0, setting the rif ?ag, so the reception of further bytes is allowed. the bit rof is not set because rstf stays set. this bit can be set in conjunction of rar to implement a circular buffer. roe = 0 means no over?ow enable. roe = 1 means over?ow enable. 3 rof reception over?ow ?ag . this ?ag is set by the queue controller, when a character is received with the rstf ?ag reset and ren set. this event can occur after the end of reception of a frame, and if the cpu had no time to unload the ram and set rstf. rof = 0 means no over?ow detection. rof = 1 means over?ow.
1996 dec 11 43 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 12.3.2 t ransmission c ontrol r egister and i nterrupt f lags (uqtc) table 57 transmission control register and interrupt flags (address ffff 8b01h) notes 1. cpu. r: the cpu can reset this bit. s: the cpu can set this bit. 2. queue. r: the queue controller can reset this bit. s: the queue controller can set this bit. table 58 description of uqtc bits 2 rar reception address reset . if this ?ag is set, when the buffer size has been decremented to zero, the reception address is reset. this way a circular reception buffer can be located at address 0. rar = 0 means no reset of reception address. rar = 1 means reset of reception address. 1 rhlt reception halt . this bit is set by the cpu to interrupt the reception of the frame. the byte currently received by the uart will be stored in the buffer, but the next bytes will be lost until the cpu reset the bit rhlt. in order to stop all activity in the uart it is preferable to reset the bit ren reception enable of the register scon0. rhlt = 0 means reception not halted. rhlt = 1 means reception halted. 0 rstf reception start ?ag . this bit is set by the cpu to enable the reception of a frame through the uart and it is reset automatically by the queue controller at the end of reception. when rhlt is set this bit stays set. when ren is reset, this bit is reset. rstf = 0 means reception not started or ended. rstf = 1 means reception started and in progress. action of bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tif rif reserved tiwf ten tie thlt tstf cpu (1) rr -- s/r s/r s/r s queue (2) ss - s/r --- r bit symbol description 7 tif transmission interrupt ?ag . this ?ag is set either at the end of the transmission buffer or at the transmission of each byte if tie is set. the tif ?ag should be reset by the cpu in the exception routine in order to detect further interrupts as they are edge detected for low-to-high transitions. 6 rif reception interrupt ?ag . this ?ag is set either at the end of the reception buffer or during a character match if rme is set or at the reception of each byte if rie is set. the rif ?ag should be reset by the cpu in the exception routine in order to detect further interrupts as they are edge detected for low-to-high transitions. 5 - reserved. 4 tiwf transmission interrupt waiting . tiwf = 0 (1) means queue controller is not waiting for uart transmit interrupt.tiwf = 1 means queue controller is waiting for uart transmit interrupt. 3 ten transmission queue enable . ten = 0 (1) means transmission queue disable. transmitted byte can be written directly into sbuf0. ten = 1 means transmission queue enable; the transfers from the ram to sbuf0 can be activated by setting the bit tstf. bit symbol description
1996 dec 11 44 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) note 1. state after peripheral reset. 12.3.3 uart q ueue r egisters table 59 uart queue registers 2 tie transmission interrupt enable . if it is set, each time a byte is transmitted the transmit interrupt ?ag tif is set. if it is not set, an interrupt is only generated at the end of the frame. tie = 0 (1) means no interrupt after the reception of each byte. tie = 1 means interrupt after the reception of each byte. 1 thlt halt transmission . this bit is set by the cpu to interrupt the transmission of the frame. the byte currently loaded in the uart will be transmitted entirely, but the next byte will wait until the cpu reset the bit hltt. thlt = 0 (1) means transmission not halted. thlt = 1 means transmission halted. 0 tstf start transmission . this bit is set by the cpu to start the transmission of a frame through the uart and it is reset automatically by the queue controller at the end of transmission. tstf = 0 (1) means transmission not started or ended. tstf = 1 means transmission started and in progress. register address 76543210 uqta ffff 8b03h a7 a6 a5 a4 a3 a2 a1 a0 uqts ffff 8b05h s7 s6 s5 s4 s3 s2 s1 s0 uqra ffff 8b07h a7 a6 a5 a4 a3 a2 a1 a0 uqrs ffff 8b09h s7 s6 s5 s4 s3 s2 s1 s0 uqrm ffff 8b0bh m7 m6 m5 m4 m3 m2 m1 m0 bit symbol description
1996 dec 11 45 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 12.3.4 uart queue operation :t ransmission the uart queue transmit operation is as follows: 1. the uart control register is initialized for a certain transmission mode (0, 1, 2 and 3) and the baud rate generator loaded for a defined baud rate. 2. the cpu loads the data to be transmitted (for example 80 characters) at successive addresses of the internal ram starting at a certain base address (for example ffff 9010h). then it writes the buffer start address and the buffer size in the pointer registers, and initializes the control register. 3. the queue controller reads the byte at the address pointed by the address register and writes it to the transmit data buffer of the uart and the buffer size register is decremented, the address register is incremented pointing to the next byte in the buffer. the transmission starts. the controller waits for the end of transmission, then compares the buffer size value to zero, if they are not equal the same operation is repeated automatically. 4. if the buffer size is zero the transmit interrupt flag tif is set issuing an interrupt to the cpu.the interrupt routine should reset tif and can reload the buffer with other values. 5. before checking the buffer size value, the halt bit thlt is tested and if it is set the controller enters a transmission wait state. table 60 transmission routine 12.3.5 uart queue operation :r eception the uart queue reception operation is as follows: the uart control register is initialized for a certain reception mode (mode 0, 1, 2 and 3) and the baud rate generator loaded for a defined baud rate. the cpu writes the buffer start address and the buffer size in the data registers, and the control register. several modes can be used: move.b #$50,uqts ;buffer size move.b #$10,uqta ;buffer start address bset ten,uqtc; ;enable transmission queue bset stf,uqtc; ;start transmission. 12.3.5.1 mode 0: normal reception buffer. we want to receive 80 characters, store then in a buffer starting at the address ffff 9020h and generate an interrupt. the cpu is able to down-load the 80 characters, before the reception of any further character. after reception of the first character the queue controller reads the data reception register sbuf0 and transfers its contents into the buffer at the address of the uqra register, at the same time the buffer size register uqrs is decremented, the address register uqra is incremented to point to the next byte. if the buffer size is not equal to zero the same operation is repeated automatically for the next byte to be transmitted. if the buffer size is zero the receive interrupt flag rif is set issuing an interrupt to the cpu. the interrupt routine should reset rif and can read the content of the buffer and re-initialize the control registers. table 61 reception routine table 62 interrupt routine move.b #$50, uqrs ;set buffer size move. #$20, uqra ;set buffer start address bset ren, uqrc ;enable queue controller bset rstf, uqrc ;start reception. move.b #$be,uqtc ;reset rif bit move.b #$28,d0 ;buffer size in words move.l #$ffff9020,a0 ;buffer start address l1 move.l #$00008000,a1 ;external memory start address dbne d0,l1 ;loop
1996 dec 11 46 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 12.3.5.2 mode 1: special termination character match. suppose that we want to generate an interrupt after the reception of a carriage return character, we load in the reception match register the value 0dh, to guarantee that the buffer does not overflow if the buffer size is limited to 80 characters. the buffer is located in ram at the address ffff 9050h. the same operations as described before are performed but in addition each received characters compared with the character carriage return and if they match the receive interrupt flag rif is set, rstf is reset and the reception queue is stopped. table 63 mode 1 routine note 1. all these control bits can be set at the same time. 12.3.5.3 mode 2: linear buffer with continuous reception. if we want to continue to receive characters in the buffer after the end of the buffer and the setting of rif: in this case rstf is not reset at the end of the buffer, but the cpu will receive an interrupt (rif = 1) when the size register uqrs equals zero. table 64 mode 2 routine note 1. all these control bits can be set at the same time. move.b #$50,uqrs ; buffer size move.b #$50,uqra ; buffer start address move.b #$0d,uqrm ; set match character bset ren,uqrc ; enable queue bset rme,uqrc ; reception match enable bset rstf,uqrc ; start reception (note 1) move.b #$50,uqrs ; buffer size move.b #$50,uqra ; buffer start address bset ren,uqrc ; enable queue bset roe,uqrc ; reception over?ow enable bset rstf,uqrc ; start reception (note 1) 12.3.5.4 mode 3: circular buffer with interrupt. if we want to implement a circular buffer which generates an interrupt each time the size register is equal to 0, the uqra address register is reset and points to the beginning of the ram. table 65 mode 3 routine note 1. all these control bits can be set at the same time. 12.3.6 uart queue operation :r eception halt before to check the buffer size value, the halt bit hltr0 is tested and if it is set the controller enters a reception wait state. 12.3.7 uart queue operation :e mulation when the pin phalt (on the emulation package) is asserted low, the queue is halted the same way as when thlt and rhlt are set. the queue operation is continued when the pin phalt is released high. move.b #$50,uqrs ; buffer size move.b #$00,uqra ; buffer start address bset ren,uqrc ; enable queue bset rar,uqrc ; reception reset address bset rstf,uqrc ; start reception (note 1)
1996 dec 11 47 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 12.4 i 2 c-bus interface the serial port supports the twin line i 2 c-bus. the i 2 c-bus consists of a data line sda and a clock line scl. these lines also function as i/o port lines p11 and p10 respectively (always open drain). the system is unique because data transport, clock generation, address recognition and bus control arbitration are all controlled by hardware. the i 2 c-bus serial i/o has complete autonomy in byte handling and operates in four modes: master transmitter mode master receiver mode slave transmitter mode slave receiver mode. these functions are controlled by the scon register. ssta is the status register whose contents may be used as a vector to various service routines. sdat is the data shift register and sadr the slave address register. slave address recognition is performed by hardware. for more details on the i 2 c-bus functions, see user manual the i 2 c-bus and how to use it (including specifications) ; order number 9398 393 40011. 12.5 serial control register (scon) table 66 serial control register (address ffff 8207h) table 67 serial control register scon bits 7 6 5 4 3 2 1 0 cr2 ens sta sto si aa cr1 cr0 bit symbol description 7, 1 and 0 cr2 to cr0 these three bits determine the serial clock frequency when sio is in a master mode function of the peripheral clock fclk (see tables 68 and 69). 6 ens enable serial i/o . if ens = 0, the serial interface i/o is disabled and reset; if ens = 1, the serial interface is enabled. 5sta start flag . when this bit is set in slave mode, the hardware checks the i 2 c-bus and generates a start condition if the bus is free or after the bus becomes free. if the device operates in master mode it will generate a repeated start condition. 4sto stop flag . if this bit is set in the master mode a stop condition is generated. a stop condition detected on the i 2 c-bus clears this bit. the stop bit may also be set in slave mode in order to recover from an error condition. in this case no stop condition is generated to the i 2 c-bus, but the hardware releases the sda and scl lines and switches to the not selected slave receiver mode. the stop ?ag is cleared by the hardware. 3si serial interrupt flag . this flag is set, and an interrupt is generated, after any of the following events occur: a start condition is generated in master mode. the own slave address has been received during aa = 1. the general call address has been received while bit sadr.0 = 1 and aa = 1. a data byte has been received or transmitted in master mode. a data byte has been received or transmitted as selected slave. a stop or start condition is received as selected slave receiver or transmitter. while the si ?ag is set, scl remains low and the serial transfer is suspended. si must be reset by software.
1996 dec 11 48 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) table 68 clk/scl divide factor values greater than 100 kbits are outside the specified frequency range. table 69 i 2 c-bus serial clock rates values greater than 100 kbits are outside the specified frequency range. note to tables 68 and 69 1. d = divisor = clk fclk ; see table 15. 2aa assert acknowledge when this bit is set, an acknowledge is returned after any one of the following conditions: slave address is received. the general call address is received (bit sadr.0 = 1). a data byte is received, while the device is programmed to be a master receiver. a data byte is received, while the device is a selected slave receiver. when bit aa is reset, no acknowledgement is returned. consequently, no interrupt is requested when the own slave address or general call address is received. cr2 cr1 cr0 clk/scl divide factor d=2 (1) d = 3 d = 4 d = 5 d=6 d=8 d=10 0 0 0 128 192 256 320 384 512 640 0 0 1 112 168 224 280 336 448 560 0 1 0 96 144 192 240 288 384 480 0 1 1 80 120 160 200 240 320 400 1 0 0 480 720 960 1200 1440 1920 2400 1 0 1 60 90 120 150 180 240 300 1 1 0 30 45 60 75 90 120 150 cr2 cr1 cr0 bit frequency (khz) at clk = 26 mhz d=2 (1) d=3 d=4 d=5 d=6 d=8 d=10 000 -- 101 81 68 51 41 001 --- 93 77 58 46 010 ---- 90 68 54 011 ----- 81 65 1 0 0 54 36 27 22 18 13 10 101 ------ 87 110 ------- bit symbol description
1996 dec 11 49 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 12.5.1 i 2 c- bus s tatus r egister (ssta) ssta is an 8-bit read only special function register. the contents of ssta may be used as a vector to a service routine. this optimizes response time of the software and consequently that of the i 2 c-bus. tables 73 to 77 show the list of the status codes defined by the contents of register ssta. table 70 i 2 c-bus status register (address ffff 8205h) table 71 description of ssta bits table 72 used abbreviations in the mode descriptions; see tables 73 to 77 table 73 master transmitter (mst/trx) mode 7 6 5 4 3 2 1 0 sc4 sc3 sc2 sc1 sc0 --- bit symbol description 7 to 3 sc4 to sc0 the bits sc4 to sc0 hold a status code. 2to0 - reserved; held low. symbol description sla 7-bit slave address r read bit w write bit ack acknowledgement (acknowledge bit = 0) acknot not acknowledge (acknowledge bit = 1) data 8-bit (byte) to or from the i 2 c-bus mst master slv slave trx transmitter rec receiver ssta value description 08h a start condition has been transmitted 10h a repeated start condition has been transmitted 18h sla and w have been transmitted, ack has been received 20h sla and w have been transmitted, acknot received 28h data of s1dat has been transmitted, ack received 30h data of s1dat has been transmitted, acknot received 38h arbitration lost in sla, r/ w or data
1996 dec 11 50 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) table 74 master receiver (mst/rec) mode table 75 slave transmitter (slv/trx) mode table 76 slave receiver (slv/rec) mode table 77 miscellaneous ssta value description 38h arbitration lost while returning acknot 40h sla and r have been transmitted, ack received 48h sla and r have been transmitted, acknot received 50h data has been received, ack returned 58h data has been received, acknot returned s1sta value description a8h own sla and r received, ack returned b0h arbitration lost in sla, r/ w as mst. own sla and r received, ack returned b8h data byte has been transmitted, ack received c0h data byte has been transmitted, ack received c8h last data byte has been transmitted, acknot received ssta value description 60h own sla and w have been received, ack returned 68h arbitration lost in sla, r/ w as mst. own sla and w have been received, ack returned 70h general call has been received, ack returned 78h arbitration lost in sla, r/ w as mst. general call received, ack returned 80h previously addressed with own sla. data byte received, ack returned 88h previously addressed with own sla. data byte received, acknot returned 90h previously addressed with general call. data byte received, ack has been returned 98h previously addressed with general call. data byte received, acknot has been returned a0h a stop condition or repeated start condition received while still addressed as slv/rec or slv/trx s1sta value description 00h bus error during mst mode or selected slv mode, due to an erroneous start or stop condition
1996 dec 11 51 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 12.5.2 i 2 c- bus d ata s hift r egister (sdat) table 78 i 2 c-bus data shift register (address ffff 8201h) table 79 description of sdat bits 12.5.3 i 2 c- bus a ddress r egister (sadr) this 8-bit register may be loaded with the 7-bit address to which the controller will respond when programmed as a slave receiver/transmitter. table 80 i 2 c-bus address register (address ffff 8203h) table 81 description of sadr bits 7 6 5 4 3 2 1 0 data.7 data.6 data.5 data.4 data.3 data.2 data.1 data.0 bit symbol description 7 to 0 data.7 to data.0 the serial data to be transmitted or data that has just been received. bit 7 is transmitted or received ?rst; i.e. data is shifted from right to left. 7 6 5 4 3 2 1 0 sadr.7 sadr.6 sadr.5 sadr.4 sadr.3 sadr.2 sadr.1 sadr.0 bit symbol description 7 to 1 sadr.7 to sadr.1 slave address. 0 sadr.0 sadr.0 = gc, is used to determine whether the general call address is recognized. if gc = 0, general call address is not recognized (default value after a cpu reset). if gc = 1, general call address is recognized.
1996 dec 11 52 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 13 pulse width modulation (pwm) outputs two pulse width modulation outputs are provided on the P90CL301. these channels output pulses of programmable length and interval. the repetition frequency is defined by an 8-bit prescaler pwmp, which generates the clock for the counter. the 8-bit counter counts modulo 255 (from 0 to 254 inclusive). the prescaler and counter are used for the two channel outputs. the value of the 8-bit counter is compared to the content of the registers pwm0 (resp. pwm1) for the channel output pwm0 (resp. pwm1). provided the content of this register is greater than the counter value, the output of pwm0 (resp. pwm1) is set low. if the content of this register is equal to, or less than the counter value, the output will stay high. the pulse width ratio is therefore defined by the content of the register pwm0 (respectively pwm1). the pulse width ratio is in the range of 0 to 255 255 and may be programmed in increments of 1 255 . the repetition frequency: ; for fclk in hz. when using a peripheral clock of 6 mhz for example, the above formula gives a repetition frequency range of 23 khz to 91 hz. by loading the pwm0 (resp. pwm1) with either 00h or ffh, the pwm0 output can be retained at a constant high or low level respectively. when loading ffh to the pwm0 (respectively pwm1) register, the 8-bit counter will never actually reach this value. f pwm fclk 1 pwmp + () 255 --------------------------------------------------- hz = 13.1 prescaler pwm register (pwmp) table 82 prescaler pwm register (address ffff 8801h) table 83 description of pwmp bits 13.2 pwm data registers (pwm0 and pwm1) table 84 pwm data registers pwm0 and pwm1 table 85 description of pwm0 and pwm1 bits; n = 0 to 1 7 6 5 4 3 2 1 0 pwmp.7 pwmp.6 pwmp.5 pwmp.4 pwmp.3 pwmp.2 pwmp.1 pwmp.0 bit symbol description 7 to 0 pwmp.7 to pwmp.0 prescaler division factor = (pwmp + 1). address register 7 6 5 4 3 2 1 0 ffff 8803h pwm0 pwm0.7 pwm0.6 pwm0.5 pwm0.4 pwm0.3 pwm0.2 pwm0.1 pwm0.0 ffff 8805h pwm1 pwm1.7 pwm1.6 pwm1.5 pwm1.4 pwm1.3 pwm1.2 pwm1.1 pwm1.0 bit symbol description 7 to 0 pwmn.7 to pwmn.0 pulse width ratio. low/high ratio of pwmn signals pwmn () 255 pwmn () C ----------------------------------------- - =
1996 dec 11 53 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) fig.13 pwm block diagram. n dbook, full pagewidth mbg326 i n t e r n a l b u s fclk pwm1 register pwmp 8-bit prescaler 8-bit counter pwm0 register 8-bit comparator 8-bit comparator output buffer pwm1 output buffer pwm0
1996 dec 11 54 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 14 analog-to-digital converter (adc) the analog input circuitry consist of a 4 input analog multiplexer and an analog-to-digital converter (adc) with 8-bit resolution. the analog reference voltage v ref(a) and the analog supplies v dda , v ssa are connected via separate input pins. the conversion time takes 24 periods of the secondary peripheral clock fclk2 (see section 6.6). the maximum value of the fclk2 clock is dependant on the supply voltage (see section 20). as the adc is based on a successive approximation algorithm using a resistor scale connected to v ref(a) and v ssa , a continuous current flows in this resistor. by resetting the eadc bit in the control register adcon or by entering power-down it is possible to switch off this current to reduce the static power consumption. the adc is controlled using the adcon control register. input channels are selected by the analog multiplexer function of register bits adcon.0 and adcon.1. the completion of the 8-bit adc conversion is flagged by adci in the adcon register and the result is stored in the register adcdat (address ffff 8809h). the result of a completed conversion remains unaffected provided adci is high. while adcs or adci are high, a new adc start will be blocked and consequently lost. an adc conversion already in progress is aborted when power-down mode is entered. 14.1 adc control register (adcon) table 86 adc control register (address ffff 8807h) table 87 description of adcon bits table 88 operation of adci and adcs 7 6 5 4 3 2 1 0 - eadc - adci adcs - a1 a0 bit symbol description 7, 5 and 2 - reserved; set to low. 6 eadc adc enable . if eadc = 1, then adc is enabled. if eadc = 0, then adc is disabled; the resistor reference is switched off to save power even while the cpu is operating. 4 adci adc interrupt ?ag . this ?ag is set when an adc conversion result is ready to be read. an interrupt is invoked if the level ipla is different from 0. the ?ag must be cleared by software (it cannot be set by software). the adci bit must be cleared before a new conversion is started. 3 adcs adc start and status . setting this bit starts a conversion. the logic ensures that this signal is high while the conversion is in progress. on completion, adcs is reset at the same time the interrupt ?ag adci is set. adcs cannot be reset by software. 1, 0 a1, a0 analog input select . this binary coded address selects one of the four analog inputs adc0 to adc3. it can only be changed when adci and adcs are both low. a1 is the msb; e.g. 11 selects analog input channel adc3. adci adcs operation 0 0 adc not busy, a conversion can be started. 0 1 adc busy, start of a new conversion is blocked. 1 0 conversion completed, start of a new conversion is blocked. 1 1 intermediate status for a maximum of one machine cycle before conversion is completed (adci = 1, adcs = 0).
1996 dec 11 55 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) fig.14 functional diagram of the adc. handbook, full pagewidth mgd779 ad0 analog input multiplexer 8-bit analog-to-digital converter (succesive approximation) adcon start end a0 a1 adcs eadc adci 12 34567 0 1-34-6- 0 v ref(a) v dda v ssa + adcdat pd (syscon.2) logic internal bus ad1 ad2 ad3 - +
1996 dec 11 56 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 15 on-board test concept to improve the on-board debugging two functions are implemented, the on-circuit emulation (once) mode and the on-chip test-rom. 15.1 once mode the on-circuit emulation (once) mode eases the testing of an application without having to remove the controller from the board. the once mode is entered by pulling csbt low during reset. in this mode the address bus, data bus and bus control signals are in 3-state mode, all other output or bidirectional pins are weakly pulled high. in this mode an emulator probe can be hooked-up to the circuit. normal operation is restored with a normal reset. 15.2 test-rom a second on-board debugging function is introduced for the situation where no extra connector can be placed on the pcb. it consists of an internal test-rom of 256 bytes which is used as boot rom after a special test mode is activated during reset. the cpu will execute the code placed in the test-rom and initialize the uart0 and its baud rate generator and wait for commands to be sent to uart0. the internal access time is in this case 3 cycles long. it can only be accessed in supervisor mode. the purpose of the test-rom is to offer the user a simple software interface to load programs for testing its own application and to transmit back the test result. the program can be loaded from the host into either the on-chip ram or the external memory. the test-rom mode is entered by pulling low the r/ w / trom pin during reset. just after the reset initialization, the user should send a character of 9 bits (one stop bit plus eight data bits) with all bits being zero, on the rx0 line. using the timer, the character length is captured and then the baud rate is automatically calculated and the baud rate generator is initialized. the uart0 is then initialized in mode 3 with sm2 multiprocessor bit set, ren and tb8 bit set (scon = f8h). the hardware is now ready to handle the protocol using the following 4 commands (code 00 to 11). table 89 command format table 90 command description 7 6 5 4 3 2 1 0 code nb byte - 1 bit symbol description 7, 6 code pointer commands; see table 91. 5 to 0 nb byte - 1 indicates the length of the transfer; e.g. (nb byte - 1) = 0 means a 1 byte transfer, (nb byte - 1) = 63 means a 64 byte transfer.
1996 dec 11 57 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) table 91 pointer commands 16 on-chip ram the P90CL301bfh contains a 512 bytes ram which can be used to store program code or data. as this memory does not need wait states, it can speed up some time consuming tasks like stack operation, table references, or small program loops, compared with slow external memory or when using the 8-bit data bus. for a read or write access, 3 cpu clocks are used. the memory content is kept even when the supply voltage is lowered down to 1.8 v after entering power-down mode. the base address is ffff 9000h. it can be accessed in long word, word or bytes. code description bit 7 bit 6 0 0 the pointer (a0 register) is initialized with a value depending of the number of transferred bytes. the most significant byte should be transferred first. protocol: to start a data transfer, the pointer should be initialized ?rst. it is incremented by one at each byte transfer between the memory and the host. the following registers are reserved for the protocol and should not be used by the user: d0, d1, d2, d3, a0, a1 and a2. 0 1 read command. read 1 to 64 bytes (load to the host). the pointer is incremented at each transfer. 1 0 write command. write 1 to 64 bytes (load from the host). the pointer is incremented at each transfer. 1 1 jump command. if the nb ?eld is 0 then a jump to the pointer address (a0) is done to start code execution. if the nb ?eld 1 0, the complete protocol initialization is restarted (same effect as reset and r/ w / trom = 0). fig.15 test-rom: timing data transfer. handbook, full pagewidth reset halt r/w / trom rx0 9 bits command/data write data baud rate calculation tx0 mbg333
1996 dec 11 58 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 17 register mapping the internal register map of the P90CL301bfh is summarized in table 92. note that the internal registers can be accessed: only in supervisor mode for version P90CL301bfh-3/4 both in supervisor and user mode for version P90CL301bfh-5. table 92 register map address (hex) symbol width (1) state after reset (hex) (2) register access (3) system register ffff 8000 syscon w 00c0 system control register r/w interrupt registers ffff 8101 lir0 b 00 latched interrupt 0/1 register r/w ffff 8103 lir1 b 00 latched interrupt 2/3 register r/w ffff 8105 lir2 b 00 latched interrupt 4/5 register r/w ffff 8107 lir3 b 00 latched interrupt 6/7 register r/w ffff 810f pifr b 00 pending interrupt flag register r/c i 2 c-bus registers ffff 8201 sdat b 00 i 2 c-bus data register r/w ffff 8203 sadr b 00 i 2 c-bus address register r/w ffff 8205 ssta b f8 i 2 c-bus status register r ffff 8207 scon b 00 i 2 c-bus control register r/w timers registers ffff 8300 t0crh b/w 0000 timer 0 control register (high byte) r/w ffff 8301 t0crl b 00 timer 0 control register (low byte) r/w ffff 8302 t0rr w 0000 timer 0 reload register w ffff 8304 t0 w 0000 timer 0 register r ffff 8306 t0c0 w xxxx timer 0 channel 0 register r/w ffff 8308 t0c1 w xxxx timer 0 channel 1 register r/w ffff 830a t0c2 w xxxx timer 0 channel 2 register r/w ffff 830d t0sr b x 0 timer 0 status register r/c ffff 830f t0pr b 00 timer 0 prescaler reload register w ffff 8310 t1crh b/w 0000 timer 1 control register (high byte) r/w ffff 8311 t1crl b 00 timer 1 control register (low byte) r/w ffff 8312 t1rr w 0000 timer 1 reload register w ffff 8314 t1 w 0000 timer 1 register r ffff 8316 t1c0 w xxxx timer 1 channel 0 register r/w ffff 8318 t1c1 w xxxx timer 1 channel 1 register r/w ffff 831a t1c2 w xxxx timer 1 channel 2 register r/w ffff 831d t1sr b x 0 timer 1 status register r/c
1996 dec 11 59 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) ffff 831f t1pr b 00 timer 1 prescaler reload register w ffff 8401 wdtim b 00 watchdog timer register r/w ffff 8403 wdcon b a5 watchdog control register (only a5h or 5ah) s port registers ffff 8503 pcon b 00 port control register r/w ffff 8505 prl b ff p port latch (least signi?cant byte) r/w ffff 8507 ppl b ff p port pin (least signi?cant byte) r ffff 8509 prh b ff p port latch (most significant byte) r/w ffff 850b pph b ff p port pin (most signi?cant byte) r ffff 8109 spcon b 80 sp port control register r/w ffff 810b spr b ff sp port latch r/w ffff 810d spp b ff sp port pin r uart registers ffff 8601 sbuf0 b xx uart0 transmit/receive register r/w ffff 8603 scon0 b 00 uart0 control register r/w ffff 8605 sbuf1 b xx uart1 transmit/receive register r/w ffff 8607 scon1 b 00 uart1 control register r/w baud rate generator registers ffff 860b bregl b 00 uart baud rate register (least signi?cant byte) r/w ffff 860d bregh b 00 uart baud rate register (most signi?cant byte) r/w ffff 860f bcon b 00 uart baud rate control register r/w peripheral interrupt registers ffff 8701 picr0 b 00 timer interrupt register r/w ffff 8703 picr1 b 00 uart0 interrupt register r/w ffff 8705 picr2 b 00 uart1 interrupt register r/w ffff 8707 picr3 b 00 i 2 c and adc interrupt register r/w pulse width modulation registers ffff 8801 pwmp b 00 pwm prescaler register w ffff 8803 pwm0 b 00 pwm0 data register r/w ffff 8805 pwm1 b 00 pwm1 data register r/w adc registers ffff 8807 adcon b 00 adc control register r/w ffff 8809 adcdat b ff adc data register r chip-select registers ffff 8a00 cs0n w ffff chip-select 0 control register r/w address (hex) symbol width (1) state after reset (hex) (2) register access (3)
1996 dec 11 60 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) notes 1. width when specified is in byte (b) or word (w). 2. x = dont care. 3. access when specified is in read (r) write (w) or clear (c) only. the watchdog control register is special (s). ffff 8a02 cs1n w ffff chip-select 1 control register r/w ffff 8a04 cs2n w ffff chip-select 2 control register r/w ffff 8a06 cs3n w ffff chip-select 3 control register r/w ffff 8a08 cs4n w ffff chip-select 4 control register r/w ffff 8a0a cs5n w ffff chip-select 5 control register r/w ffff 8a0c cs6n w ffff chip-select 6 control register r/w ffff 8a0e csbt w f306 chip-select boot control register r/w ffff 8a11 bsreg b 00 bus size register r/w uart queue registers ffff 8b00 uqrc b 00 uart queue receive control register r/w ffff 8b01 uqtc b 00 uart queue transmit control register r/w ffff 8b03 uqta b 00 uart queue transmit address register r/w ffff 8b05 uqts b 00 uart queue transmit status register r/c ffff 8b07 uqra b 00 uart queue receive address register r/w ffff 8b09 uqrs b 00 uart queue receive status register r/c ffff 8b0b uqrm b 00 uart queue receive match register r/w address (hex) symbol width (1) state after reset (hex) (2) register access (3)
1996 dec 11 61 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 18 limiting values in accordance with the absolute maximum rating system (iec 134). 19 dc characteristics v dd = 2.7 to 3.6 v; v ss =0v; t amb = - 40 to +85 c; all voltages with respect to v ss unless otherwise speci?ed. symbol parameter min. max. unit v dd supply voltage - 0.5 +3.6 v v i input voltage on any pin with respect to ground (v ss ) - 0.5 v dd + 0.5 v i i , i o dc current into any input or output - 5ma p tot total power dissipation - 300 mw t stg storage temperature range - 65 +150 c t amb operating ambient temperature range - 40 +85 c t j operating junction temperature range - +125 c symbol parameter conditions min. typ. max. unit supply v dd supply voltage 2.7 - 3.6 v i dd supply current operating; note 1 v dd = 3 v; clk = 13.8 mhz - 16 22 ma v dd =3v; clk=27mhz - 32 40 ma i dd(id) supply current idle mode; note 2a v dd = 3 v; clk = 13.8 mhz - 400 500 m a v dd =3v; clk=27mhz - 800 1000 m a i dd(stb) supply current standby mode; note 2b v dd = 3 v; clk = 13.8 mhz - 915ma v dd =3v; clk=27mhz - 18 25 ma i dd(pd) supply current power-down mode; note 3 v dd =3v - 240 m a inputs v il low level input voltage v ss - 0.3v dd v v il low level input voltage; d15 to d8, xtal1, hal t, reset, resetin v ss - 0.1v dd v v ih high level input voltage 0.7v dd - v dd v i il low level input current v dd =3v; v in = 0.4 v - 13 50 m a i tl input current high-to-low transition v dd =3v; v in = 0.5v dd - 140 500 m a i tsi 3-state input current - 110 m a outputs i oh4 high level output current; ts4 and od4; note 4 v dd =3v; v oh =v dd - 0.4 v 4 13 - ma i oh2 high level output current ; wp2; note 4 v dd =3v; v oh =v dd - 0.4 v 2 7 - ma i ol8 low level output current; od8 and s8; note 4 v dd =3v; v ol = 0.4 v 8 24 - ma i ol4 low level output current; ts4 and od4; note 4 v dd =3v; v ol = 0.4 v 4 15 - ma i ol2 low level output current; wp2; note 4 v dd =3v; v ol = 0.4 v 2 8 - ma c in input capacitance; note 5 -- 10 pf
1996 dec 11 62 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) notes 1. the operating supply current through v dd1 , v dd2 and v dd3 is measured with all output pins disconnected; resetin = reset = halt = 0; a23 to a0 = v dd ; d15 to d0 = v dd . 2. idle and standby current: a) the idle supply current through v dd1 , v dd2 and v dd3 is measured with all port pins disconnected; a23 to a0 = v dd ; d15 to d0 = v dd ; the circuit is executing nop instructions from an external memory. b) the standby current through vdd1, vdd2 and vdd3 is measured with all port pins disconnected; a23 to a0 = vdd; d15 to d0 = vdd; 3. the power-down current through v dd1 , v dd2 and v dd3 is measured with all output pins disconnected; xtal1 = reset = haltn = v dd ; a23 to a0 = v dd ; d15 to d0 = v dd ; resetin = v ss . 4. see table 95 for the different types. 5. not tested in production. 6. pull-ups: a) these pull-ups are only present on the emulation pins phalt and nmine. b) these active pull-ups are active on all wp2 wp4 port pins for output voltages greater than vdd/2. they are only active during the reset sequence on the pins cs0, cs1, r/ w, csbt and fetch for test purpose. c) these active pull-ups are only active on d15 to d0 and a23 to a0 pins when bpe is set in the syscon register. r up pull-up resistor up; note 6a 16 26 60 k w r up2 pull-up resistor up2; note 6b 8 15 30 k w r up3 pull-up resistor up3; note 6c 70 100 500 k w r stin resetin resistor 15 31 120 k w symbol parameter conditions min. typ. max. unit
1996 dec 11 63 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 20 adc characteristics v dd = 2.7 to 3.6 v; v ref(a) =v dda =v dd ; v ssa =v ss ; v ss = 0 v; fclk2 = 250 khz to 2 mhz; t amb = - 40 to +85 c; for adc test conditions see note 1; all voltages with respect to v ss unless otherwise speci?ed. notes 1. adc test conditions: v dd = 2.7 v, v ref(a) = 2.7 v, clk = 20 mhz, fclk2 = 2 mhz . 2. this resistor is switched off during power-down mode and when the adc is switched off (eadc = 0). 3. parameter not measured in production, only verified on sampling basis. 4. see fig.17 for specific fclk2 range as function of v dd . 5. absolute voltage error: the maximum difference between actual and ideal code transitions. absolute voltage error accounts for all deviations of an actual converter from an ideal converter. 6. offset error: the difference between the actual and ideal input voltage corresponding to the first actual code transition. 7. integral non-linearity: the maximum deviation between the edges of the steps of the transfer curve and the edges of the steps of the ideal curve. the ideal step curve follows the line of least squares. 8. differential non-linearity: the maximum deviation of the actual code width from the average code width. 9. channel-to-channel matching: the difference between corresponding code transitions of actual characteristics taken from different channels under the same temperature, voltage and frequency conditions. symbol parameter conditions min. typ. max. unit v dda analog supply voltage v dd - 0.2 - v dd + 0.2 v v ref(a) analog reference voltage v dd - 0.2 - v dd + 0.2 v v ssa analog ground v ss - 0.2 - v ss + 0.2 v v in(a) analog input voltage 0 - v ref(a) v i dda supply current operating v dda = 3.0 v - 150 250 m a i dd(pd)(a) analog supply current power-down mode v dda = 3.0 v - 0.1 5 m a r vref resistor between v ref(a) and v ssa note 2 20 34 150 k w c ia analog input capacitance note 3 -- 12 pf i ia input leakage current v dda = 3.0 v -- 1 m a fclk2 adc clock frequency; v dda = 2.7 v; note 4 0.25 - 2 mhz t ads sampling time - 6 t fclk2 -m s t adc total conversion time - 24 t fclk2 -m s a e absolute voltage error note 1 and 5 -- 1 lsb os e offset error note 1 and 6 -- 1 lsb il e integral non-linearity note 1 and 7 -- 1 lsb dl e differential non-linearity note 1 and 8 -- 1 lsb m ctc channel-to-channel matching note 3 and 9 -- 1 lsb
1996 dec 11 64 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) fig.16 adc conversion characteristics. (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential non-linearity. (4) absolute voltage error. handbook, full pagewidth mgc758 1 2 3 4 5 6 7 250 251 252 253 254 255 0 1 2 3 4 5 250 251 252 253 254 255 av (lsb ) in ideal code out zero offset error (2) (3) (4) (1) 1 lsb (ideal) 1lsb v ref(a) v ssa C 256 ---------------------------------- - = fig.17 adc clock (fclk2) frequency range as a function of v dd . 23 2.7 4 3.6 mgd774 3 1 2 0.25 0 v dd (v) fclk2 (mhz)
1996 dec 11 65 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 21 ac characteristics v ss =0v; t amb = - 40 to +85 c; t clk = cpu clock cycle time; no fast bus cycle (fbc = 0); no wait status; all voltages with respect to v ss unless otherwise speci?ed. symbol parameter min. typ. max. unit t avsl address valid to as low 0.5t clk - 10 0.5t clk + 2 - ns t sl as/ ds low level 2.5t clk - 10 2.5t clk + 2 - ns t shaz as high to address invalid 0.5t clk - 10 0.5t clk - ns t ascsl as/ ds to cs low - 51 5 ns t ascsh as/ ds to cs high - 51 5 ns t slsh as low to ds low (write) t clk - 15 t clk t clk +15 ns t dsl ds low level (write) 1.5t clk - 10 1.5t clk +2 - ns t avrl address valid to r/ w low (write) t clk - 5 t clk - ns t clsl r/ w low to ds low (write) t clk - 10 t clk - 2 - ns t dosl data-out valid to ds low (write) 0.5t clk - 10 0.5t clk - 1 - ns t shdo as high to data-out invalid 0.5t clk - 10 0.5t clk - 3 - ns t hrpw hal t/ reset pulse width 24t clk -- ns t asldta as low to dt ack low - 1.5t clk - 28 1.5t clk - 10 ns t ashdta as high to dt ack high - 2.5t clk - 25 2.5t clk ns t dcldi dt ack low to data-in (set-up time) - t clk t clk +10 ns t datsetup as low to data-in (set-up time) - 2.5t clk - 25 2.5t clk - 20 ns t shdi as high to data invalid (hold time) 0 0 - ns t shrh as high to r/ w high (write) 0.5t clk - 5 0.5t clk - 2 - ns t shah as high to a0 high t clk - 10 t clk +3 t clk +10 ns t shawh as high to a0 (?rst byte of word cycle in 8-bit mode) 0.5t clk - 10 - 0.5t clk +10 ns t shw lds high level before write 2.5t clk - 5 2.5t clk - 2 - ns fig.18 ac testing input waveform. handbook, halfpage mla586 0.9 v 0.4 v 0.7 v 0.3 v 0.7 v 0.3 v test points dd dd dd dd dd dd
1996 dec 11 66 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 22 8051 bus timing v dd = 2.7 v to 3.6 v; v ss =0v; t amb = - 40 to +85 c; t clk = cpu clock cycle time; all voltages with respect to v ss unless otherwise speci?ed. these ac parameters are not tested in production. symbol parameter min. max. unit t rr read pulse duration 4.5t clk - 10 4.5t clk + 10 ns t ww write pulse duration 4.5t clk - 10 4.5t clk +10 ns t al address set-up time 1.5t clk - 20 - ns t la address hold time t clk - 5 - ns t rd rd to valid data input - 3.5t clk - 15 ns t dfr data ?oat after read - 2t clk - 10 ns t ld ale to valid data input - 6t clk - 20 ns t lw ale to rd wr 3t clk - 20 3t clk + 20 ns t dw data set-up time before wr 6.5t clk - 20 - ns t wd data hold time after wr 0.5t clk - 10 - ns t whlh rd wr high to ale high t clk - 10 t clk + 10 ns fig.19 input current. handbook, 4 columns mgc759 1/2v dd v dd 100 m a 500 m a i il - i l i tl
1996 dec 11 67 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 23 timing diagrams fig.20 write to 8051-compatible peripheral circuits. b ook, full pagewidth t lw t clk t ww t dw t wd t al t la data out ad15 to ad8 ad7 to ad0 xtal1 ale wr a7 to a0 a15 to a8 mbg335 fig.21 read from 8051-compatible peripheral circuits. handbook, full pagewidth t rr t rd t la t lw t dfr t ld t whlh ad7 to ad0 data in ad7 to ad0 rd t al ale mbg336
1996 dec 11 68 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) fig.22 read cycle timing 16-bit mode. handbook, full pagewidth a7 to a1 a23 to a8 as cs lds uds r/w halt reset dtack data in t avsl t sl t shaz t shaz t ascsl t ascsh t shrh t hrpw t ashdta t asldta t shdi t dcldi t datsetup mgd775
1996 dec 11 69 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) fig.23 write cycle timing 16-bit mode. handbook, full pagewidth data out t avsl t sl t shaz t shaz t slsh t shw t avrl t dosl t hrpw t asldta t ashdta t shdo t clsl t dsl t ascsl t ascsh mgd776 a7 to a1 a23 to a8 as cs lds uds r/w halt reset dtack
1996 dec 11 70 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) fig.24 read cycle timing 8-bit mode. handbook, full pagewidth t avsl t sl t shaz t ascsl t ascsh t shah t shawh t datsetup t shdi t asldta t ashdta as/lds a0 data in (no fast bus cycle, fbc = 0) mgd777 a7 to a1 a23 to a8 cs r/w dtack
1996 dec 11 71 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) fig.25 write cycle timing 8-bit mode clock timing. handbook, full pagewidth t shawh t clk t shah t clsl t dosl t shdo t asldta t ashdta t1 t2 t3 t3 t1 t2 t3 t3 t1 s0 s1 s2 s3 sb sb s4 s5 s0 s1 s2 s3 sb sb s4 s5 s0 s1 t avsl t sl t shaz t ascsl t ascsh t slsh t avrl t dsl clk a0 lds cs r/w data out dtack (no fast bus cycle, fbc = 0) word transfer mgd778 a7 to a1 a23 to a8 as
1996 dec 11 72 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 24 clock timing table 93 P90CL301bfh clock timing v dd = 2.7 v. symbol parameter min. max. unit f xtal1 input frequency 0 27 mhz t clk cycle time 37 - ns t cl pulse width low 13 - ns t ch pulse width high 13 - ns t cr rise time - 5ns t cf fall time - 5ns duty cycle 45 55 % t ch t clk ---------- - fig.26 P90CL301bfh clock timing. handbook, halfpage 0.8 v dd 0.7 v t clk t cr t cf t cl t ch mbg341
1996 dec 11 73 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 25 pin states in various modes table 94 describes the function, i/o, type and state in various modes - reset, power-down, halt, once and bpe (bus pull-up enable) - of the pins. table 94 pin states in various modes pin function i/o (1) type (2) state (3) bpe on reset pd hal t once a22 to a19 address bus o tsw4 z z z z w pcs0 to pcs3 8051 chip-select o ts4 - hz - w a18 to a1 address bus o tsw4 z z z z w ad7 to ad1 8051 data bus i/o tsw4 - zz - w d7 to d0 lower 8-bits of data bus i/o tsw4 z z z z w d15 to d8 upper 8-bits of data bus i/o tsw4 z w z z w pl7 to pl0 port pl i/o wp4 - sw w w as address strobe o ts4 h h z z - lds low data strobe o ts4 h h z z - uds upper data strobe o ts4 h h z z w a0 address 0 o tsw4 h h z z w ad0 8051 address/data 0 i/o tsw4 -- zz w r/ w read write strobe o ts4 z h z z - trom test-rom mode i up2 --- - - dt ack data transfer acknowledgement i n --- - - reset cpu peripheral reset i n --- - - peripheral reset output od od8 l z z z - resetin external power-on-reset i rs --- - - hal t reset input; halt input i n --- - - peripheral reset; fault output od od8 l z z z - bsize data bus size i n --- - - nmiack emulation nmin acknowledgement od od8 z z z z - sp0 second port pin 0 i/o wp2 w s w w - rx1 uart1 receive i/o wp2 - sw w - int0 interrupt input 0 i n --- - - sp1 second port pin 1 i/o wp2 w s w w - tx1 uart1 transmit o wp2 - sw w - int1 interrupt input 1 i n --- - - clk0 external clock timer 0 i n --- - - sp2 second port pin 2 i/o wp2 w s w w - rx0 uart0 receive i/o n --- - - int2 interrupt input 2 i n --- - - cp2 timer capture 2 i n --- - - sp3 second port pin 3 i/o wp2 w s w w - tx0 uart0 transmit i/o wp2 - sw w -
1996 dec 11 74 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) int3 interrupt input 3 i n --- - - cp3 timer capture 3 i n --- - - sp4 second port pin 4 i/o wp2 w s w w - int4 interrupt input 4 i n --- - - cp4 timer capture 4 i n --- - - sp5 second port pin 5 i/o wp2 w s w w - int5 interrupt input 5 i n --- - - cp5 timer capture 5 i n --- - - sp6 second port pin 6 i/o wp2 w s w w - int6 interrupt input 6 i n --- - - clk1 external clock timer 1 i n --- - - nmin non-maskable interrupt i n --- - - sp7 second port pin 7 i/o wp2 w s w w - p8 port ph pin 8 i/o wp2 w s w w - pwm0 pwm output 0 o wp2 - hw w - cp0 timer capture 0 i n --- - - p9 port ph pin 9 i/o wp2 w s w w - pwm1 pwm output 1 o wp2 - hw w - cp1 timer capture 1 i n --- - - xtal1 external crystal input i xi --- - - cs1 to cs0 chip-select 1 to 0 o ts4 w h z z - fc1 to fc0 function code o ts4 - sz z - tsm1 to tsm0 test mode inputs multiplexed with cs1n/0n for test purpose only. i up2 --- - - cs2 chip-select 2 o ts4 h h z z - cs3 chip-select 3 o ts4 h h z z - ale 8051 address strobe o ts4 - hz z - cs4 chip-select 4 o ts4 h h z z - rd 8051 read strobe o ts4 - hz z - cs5 chip-select 5 o ts4 h h z z - wr 8051 write strobe o ts4 - hz z - p10 port ph pin 10 i/o od8 z z z z - scl i 2 c-bus clock od od8 - zz z - p11 port ph pin 11 i/o od8 z z z z - sda i 2 c-bus data od od8 - zz z - cs6 chip-select 6 o ts4 - hz z - a23 address pin 23 o ts4 h s z z - csbt chip-select boot o ts4 w h z z - once once mode i up2 --- - - p15 to p12 port ph pins 15 to 12 i/o wp2 w w z z - pin function i/o (1) type (2) state (3) bpe on reset pd hal t once
1996 dec 11 75 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) notes to the pin states in various modes 1. i = input; o = output; i/o = bidirectional. 2. see table 95 for pin type description. 3. state of the pin in different modes reset, pd (power-down), halt, once and bpe (bus pull-up enable). a) - = not available. b) z = 3-state. c) w = weak pull-up. d) s = state logic 0 or logic 1. e) r = resistive f) h = high state. g) l = low state. 4. emulation version only. table 95 pin type description adc3 to adc0 analog inputs 3 to 0 i an --- - - v ref(a) adc reference voltage i aref z z r r - fetch (4) fetch output o ts4 w z z z - emul (4) emulation mode i up2 --- - - nmine (4) emulation nmin i up --- - - clkout (4) emulation clock output o s4 s s s s - phal t (4) emulation halt i up --- - - pin type description maximum load (pf) ts4 3-state output, normal input 100 tsw4 3-state output, normal input with internal pull-up 100 wp2 weak pull-up output, normal input 80 wp4 weak pull-up output, normal input 80 n normal input - up input with internal pull-up - up2 input with internal pull-up - od8 open drain 400 an analog input - s4 strong output 100 rs schmitt trigger input - aref analog reference input - pin function i/o (1) type (2) state (3) bpe on reset pd hal t once
1996 dec 11 76 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 26 instruction set and addressing modes the P90CL301bfh is completely code compatible with the 68000, which means that programs developed for the 68000 will run on the P90CL301bfh. this applies to both the source and object codes. the instruction set was designed to minimize the number of mnemonics that the programmer has to remember. following tables give an overview of the instruction set and the different addressing modes. table 96 instruction set; for condition codes see notes 1 to 7 mnemonic description operation condition codes xnzvc abcd add decimal with extend (destination) 10 + (source) 10 + x ? destination * u * u * add add binary (destination) + (source) ? destination * * * * * adda add address (destination) + (source) ? destination ----- addi add immediate (destination) + immediate data ? destination * * * * * addq add quick (destination) + immediate data ? destination * * * * * addx add extended (destination) + (source) + x ? destination * * * * * and and logical (destination) (source) ? destination - **00 andi and immediate (destination) immediate data ? destination - **00 asl, asr arithmetic shift (destination) shifted by < count >? destination * * * * * b cc branch conditionally if cc then pc + d ? pc ----- bchg test a bit and change ~( < bit number > ) of destination ? z ~( < bit number > ) of destination ?< bit number > of destination -- * -- bclr test a bit and clear ~( < bit number > ) of destination ? z -- * -- bra branch always pc + d ? pc ----- bset test a bit and set ~( < bit number > ) of destination ? z 1 ?< bit number > of destination -- * -- bsr branch to subroutine pc ? sp @ - ; pc + d ? pc ----- btst test a bit ~( < bit number > ) of destination ? z -- * -- chk check register against bounds if dn < 0 or dn > ( < source > ) then trap - *uuu clr clear an operand 0 ? destination - 0100 cmp compare (destination) - (source) - **** cmpa compare address (destination) - (source) - **** cmpi compare immediate (destination) - immediate data - **** cmpm compare memory (destination) - (source) - **** db cc test condition, decrement & branch if (not cc) then dn - 1 ? dn; if dn 1- 1 then pc + d ? pc ----- divs signed divide (destination) / (source) ? destination - ***0 divu unsigned divide (destination) / (source) ? destination - ***0 eor exclusive or logical (destination) ? (source) ? destination - **00 eori exclusive or immediate (destination) ? immediate data ? destination - **00 exg exchange register rx ? ry -----
1996 dec 11 77 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) ext sign extend (destination) sign - extended ? destination - **00 jmp jump destination ? pc ----- jsr jump to subroutine pc ? sp @ - ; destination ? pc ----- lea load effective address destination ? an ----- link link and allocate an ? sp @ - ; sp ? an; sp + d ? sp ----- lsl, lsr logical shift (destination) shifted by < count >? destination * * * 0 * move move data from source to destination (source) ? destination - **00 move to ccr move to condition code (source) ? ccr * * * * * move to sr move to the status register (source) ? sr * * * * * move from sr move from the status register sr ? destination ----- move usp move user stack pointer usp ? an; an ? usp ----- movea move address (source) ? destination ----- movem move multiple registers registers ? destination; (source) ? registers ----- movep move peripheral data (source) ? destination ----- moveq move quick immediate data ? destination - **00 muls signed multiply (destination) * (source) ? destination - ***0 mulu unsigned multiply (destination) * (source) ? destination - ***0 nbcd negate decimal with extend 0 - (destination) 10 - x ? destination * u * u * neg negate 0 - (destination) ? destination * * * * * negx negate with extend 0 - (destination) - x ? destination * * * * * nop no operation ------ not logical complement ~(destination) ? destination - **00 or inclusive or logical (destination) (source) ? destination - **00 ori inclusive or immediate (destination) immediate data ? destination - **00 pea push effective address destination ? sp @ ------ reset reset external devices ------ rol, ror rotate (without extend) (destination) rotated by < count >? destination - **0* roxl, roxr rotate with extend (destination) rotated by < count >? destination * * * 0 * rte return from exception sp @ + ? sr; sp @ + ? pc * * * * * rtr return and restore condition codes sp @ + ? cc; sp @ + ? pc * * * * * rts return from subroutine sp @ + ? pc ----- sbcd subtract decimal with extend (destination) 10 - (source) 10 - x ? destination * u * u * s cc set according to condition if cc then 1 ? destination; else 0 ? destination ----- mnemonic description operation condition codes xnzvc
1996 dec 11 78 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) notes 1. [] = bit number. 2. * = affected. 3. - = unaffected. 4. 0 = cleared. 5. 1 = set. 6. u = defined. 7. @ = location addressed by. stop load status register and stop immediate data ? sr; stop * * * * * sub subtract binary (destination) - (source) ? destination * * * * * suba subtract address (destination) - (source) ? destination ----- subi subtract immediate (destination) - immediate data ? destination * * * * * subq subtract quick (destination) - immediate data ? destination * * * * * subx subtract with extend (destination) - (source) - x ? destination * * * * * swap swap register halves register [ 31:16 ]? register [ 15:0 ]- **00 tas test and set an operand (destination) tested ? cc; 1 ?[ 7 ] of destination - **00 trap trap pc ? ssp @ - ; sr ? ssp @ - ; (vector) ? pc ----- trapv trap on over?ow if v then trap ----- tst test and operand (destination) tested ? cc - **00 unlk unlink an ? sp; sp @ + ? an ----- mnemonic description operation condition codes xnzvc
1996 dec 11 79 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 26.1 addressing modes table 97 data addressing modes; see notes 1 to 14 notes 1. ea = effective address. 2. an = address register. 3. dn = data register. 4. xn = address or data register used as index register. 5. n = 1 for bytes; 2 for words; 4 for long words. 6. ? = replaces. 7. sr = status register. 8. pc = program counter. 9. () = contents of. 10. d 8 = 8-bit offset (displacement). 11. d 16 = 16-bit offset (displacement). 12. sp = stack pointer. 13. ssp = system stack pointer. 14. usp = user stack pointer. mode generation register direct addressing data register direct ea = dn address register direct ea = an absolute data addressing absolute short ea = (next words) absolute long ea = (next two words) program counter relative addressing relative with offset ea = (pc) + d 16 relative with index and offset ea = (pc) + (xn) + d 8 register indirect addressing register indirect ea = (an) postincrement register indirect ea = (an), an ? an + n predecrement register indirect an ? an - n, ea = (an) register indirect with offset ea = (an) + d 16 indexed register indirect with offset ea = (an) + (xn) + d 8 immediate data addressing immediate data = next word(s) quick immediate inherent data implied addressing implied register ea = sr, usp, ssp, pc, sp
1996 dec 11 80 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 27 instruction timing in the tables 98 to 110 the number of bus read and write cycles are shown in parentheses as (r/w). the timing is given for operation in 16-bit mode. for operation in 8-bit mode the numbers shown in parentheses should be multiplied by a factor 2. table 98 effective address calculation times table 99 move byte and move word instruction clock periods instruction addressing mode byte; word long rn data or address register direct 0 (0/0) 0 (0/0) (an) address register indirect 4 (1/0) 8 (2/0) (an)+ address register indirect postincrement 4 (1/0) 8 (2/0) - (an) address register indirect predecrement 7 (1/0) 11 (2/0) d(an) address register indirect displacement 11 (2/0) 12 (3/0) d(an, xi) address register indirect with index 14 (2/0) 8 (3/0) xxx.s absolute short 8 (2/0) 12 (3/0) xxx.l absolute long 12 (3/0) 16 (4/0) d(pc) program counter with displacement 11 (2/0) 15 (3/0) d(pc, xi) program counter with index 14 (2/0) 16 (4/0) #xxx immediate 4 (1/0) 8 (2/0) instr. rn (an) (an)+ - (an) d(an) d(an, xi) xxx.s xxx.l rn 7 (1/0) 11 (1/1) 11 (1/1) 14 (1/1) 18 (1/1) 21 (1/1) 15 (1/1) 19 (1/1) (an) 11 (2/0) 15 (2/1) 15 (2/1) 18 (2/1) 22 (2/1) 25 (2/1) 19 (2/1) 23 (2/1) (an)+ 11 (2/0) 15 (2/1) 15 (2/1) 18 (2/1) 22 (2/1) 25 (2/1) 19 (2/1) 23 (2/1) - (an) 14 (2/0) 18 (2/1) 18 (2/1) 22 (2/1) 25 (2/1) 28 (2/1) 22 (2/1) 26 (2/1) d(an) 18 (3/0) 22 (3/1) 22 (3/1) 25 (2/1) 29 (2/1) 32 (2/1) 26 (2/1) 30 (2/1) d(an, xi) 21 (3/0) 25 (3/1) 25 (3/1) 28 (3/1) 32 (3/1) 35 (3/1) 29 (3/1) 33 (3/1) xxx.s 15 (3/0) 19 (3/1) 19 (3/1) 22 (3/1) 26 (3/1) 29 (3/1) 23 (3/1) 27 (3/1) xxx.l 19 (4/0) 23 (4/1) 23 (4/1) 26 (4/1) 30 (4/1) 33 (4/1) 27 (4/1) 31 (4/1) d(pc) 18 (3/0) 22 (3/1) 22 (3/1) 25 (3/1) 29 (3/1) 32 (3/1) 26 (3/1) 30 (3/1) d(pc, xi) 21 (3/0) 25 (3/1) 25 (3/1) 28 (3/1) 32 (3/1) 35 (3/1) 29 (3/1) 33 (3/1) #xxx 11 (3/0) 15 (2/1) 15 (2/1) 18 (2/1) 22 (2/1) 25 (2/1) 19 (2/1) 23 (2/1)
1996 dec 11 81 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) table 100 move long instruction clock periods table 101 standard instruction clock periods notes 1. add effective address calculation time. 2. indicates maximum value. 3. the duration of the instruction is constant. instr. rn (an) (an)+ - (an) d(an) d(an, xi) xxx.s xxx.l rn 7 (1/0) 15 (1/2) 15 (1/2) 18 (1/2) 22 (2/2) 25 (2/2) 19 (2/2) 23 (3/2) (an) 15 (2/0) 23 (2/2) 23 (2/2) 26 (2/2) 30 (4/2) 33 (4/2) 27 (4/2) 31 (5/2) (an)+ 15 (3/0) 23 (3/2) 23 (3/2) 26 (3/2) 30 (4/2) 33 (4/2) 27 (4/2) 31 (5/2) - (an) 18 (3/0) 26 (3/2) 26 (3/2) 29 (3/2) 33 (4/2) 36 (4/2) 30 (4/2) 34 (5/2) d(an) 22 (4/0) 30 (4/2) 30 (4/2) 33 (4/2) 37 (5/2) 40 (5/2) 34 (5/2) 38 (6/2) d(an, xi) 25 (4/0) 33 (4/2) 33 (4/2) 36 (4/2) 40 (5/2) 43 (5/2) 37 (5/2) 41 (6/2) xxx.s 19 (4/0) 27 (4/2) 27 (4/2) 30 (4/2) 34 (5/2) 37 (5/2) 31 (5/2) 35 (6/2) xxx.l 23 (5/0) 31 (5/2) 31 (5/2) 34 (5/2) 38 (6/2) 41 (6/2) 35 (6/2) 39 (7/2) d(pc) 22 (4/0) 30 (4/2) 30 (4/2) 33 (4/2) 37 (5/2) 40 (5/2) 34 (5/2) 38 (6/2)) d(pc, xi) 25 (4/0) 33 (4/2) 33 (4/2) 36 (4/2) 40 (5/2) 43 (5/2) 37 (5/2) 41 (6/2) #xxx 15 (3/0) 23 (3/2) 23 (3/2) 26 (3/2) 30 (4/2) 33 (4/2) 27 (4/2) 31 (5/2) instruction size op, an op, dn op, m add byte, word 7 (1) (1/0) 7 (1) (1/0) 11 (1) (1/1) long 7 (1) (1/0) 7 (1) (1/0) 15 (1) (1/2) and byte, word - 7 (1) (1/0) 11 (1) (1/1) long - 7 (1) (1/0) 15 (1) (1/2) cmp byte, word 7 (1) (1/0) 7 (1) (1/0) - long 7 (1) (1/0) 7 (1) (1/0) - divs -- 169 (1)(2) (1/0) - divu -- 130 (1)(3) (1/0) - eor byte, word - 7 (1) (1/0) 11 (1) (1/1) long - 7 (1) (1/0) 15 (1) (1/2) muls -- 76 (1)(3) (1/0) - mulu -- 76 (1)(3) (1/0) - or byte, word - 7 (1) (1/0) 11 (1) (1/1) long - 7 (1) (1/0) 15 (1) (1/2) sub byte, word 7 (1) (1/0) 7 (1) (1/0) 11 (1) (1/1) long 7 (1) (1/0) 7 (1) (1/0) 15 (1) (1/2)
1996 dec 11 82 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) table 102 immediate instruction clock periods note 1. add effective address calculation time. table 103 shift/rotate instruction clock periods note 1. add effective address calculation time. instruction size op<#>, dn op<#>, an op<#>, m addi byte, word 14 (2/0) - 18 (1) (2/1) long 18 (3/0) - 26 (1) (3/2) addq byte, word 7 (1) (1/0) 7 (1) (1/0) 11 (1) (1/1) long 7 (1) (1/0) 7 (1) (1/0) 15 (1) (1/2) andi byte, word 14 (2/0) - 18 (1) (2/1) long 18 (3/0) - 26 (1) (3/2) cmpi byte, word 14 (2/0) - 14 (2/0) long 18 (3/0) - 18 (3/0) eori byte, word 14 (2/0) - 18 (1) (2/1) long -- 26 (1) (3/2) moveq long 7 (1/0) -- ori byte, word 14 (2/0) - 18 (1) (2/1) long 18 (3/0) - 26 (1) (3/2) subi byte, word 14 (2/0) - 18 (1) (2/1) long 18 (3/0) - 26 (1) (3/2) subq byte, word 7 (1) (1/0) 7 (1/0) 11 (1) (1/1) long 7 (1) (1/0) 7 (1/0) 15 (1) (1/2) instruction size register memory asr, asl byte 13 + 3n (1/0) 14 (1/1) (1) word 13 + 3n (1/0) - lsr, lsl byte, word 13 + 3n (1/0) 14 (1/1) (1) long 13 + 3n (1/0) - ror, rol byte, word 13 + 3n (1/0) 14 (1/1) (1) long 13 + 3n (1/0) - roxr, roxl byte, word 13 + 3n (1/0) 14 (1/1) (1) long 13 + 3n (1/0) -
1996 dec 11 83 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) table 104 single operand instruction clock periods notes 1. add effective address calculation time. 2. subtract one read cycle ( - 4(1/0)) from effective address calculation. 3. subtract two read cycles ( - 8(2/0)) from effective address calculation. table 105 bit manipulation instruction clock periods note 1. add effective address calculation time. instruction size register memory clr byte, word 7 (1/0) 11 (1/1) (1)(2) long 7 (1/0) 15 (1/2) (1)(3) nbcd byte, word 10 (1/0) 14 (1/1) (1) neg byte, word 7 (1/0) 11 (1/1) (1) long 7 (1/0) 15 (1/2) (1) negx byte, word 7 (1/0) 11 (1/1) (1) long 7 (1/0) 15 (1/2) (1) not byte, word 7 (1/0) 11 (1/1) (1) long 7 (1/0) 15 (1/2) (1) scc byte, word 13 (1/0) 17 (1/1) (1) long 13 (1/0) 14 (1/1) (1) tas byte 10 (1/0) 15 (2/1) (1)(2) tst byte, word 7 (1/0) 7 (1/0) (1) long 7 (1/0) 7 (1/0) (1) instruction size dynamic static register memory register memory bchg byte - 14 (1/1) (1) - 21 (2/1) (1) long 10 (1/0) - 17 (2/0) - bclr byte - 14 (1/1) (1) - 21 (2/1) (1) long 10 (1/0) - 17 (2/0) - bset byte - 14 (1/1) (1) - 21 (2/1) (1) long 10 (1/0) - 17 (2/0) - btst byte - 7 (1/0) (1) - 14 (2/0) (1) long 7 (1/0) - 14 (2/0) -
1996 dec 11 84 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) table 106 conditional instruction clock periods note 1. add effective address calculation time. table 107 jmp, jsr, lea, pea, movem instruction clock periods n = number of registers to move. table 108 multi-precision instruction clock periods instruction display trap or branch taken not taken bcc byte 13 (1/0) 13 (1/0) word 14 (2/0) 14 (2/0) bra byte 13 (1/0) - word 14 (2/0) - bsr byte 21 (1/2) - word 22 (2/2) - dbcc cc true - 14 (2/0) cc false 17 (2/0) 17 (3/2) chk - 70 (3/4) (1) 19 (1/0) (1) trapv - 55 (3/4) 10 (1/0) instruction size (an) (an)+ - (an) d(an) d(an, xi) xxx.s xxx.l d(pc) d(pc, xi) jmp - 7 (1/0) -- 14 (2/0) 17 (2/0) 14 (2/0) 18 (3/0) 14 (2/0) 17 (2/0) jsr - 18 (1/2) -- 25 (2/2) 28 (2/2) 25 (2/2) 28 (2/2) 25 (2/2) 28 (2/2) lea - 7 (1/0) -- 14 (2/0) 17 (2/0) 14 (2/0) 18 (3/0) 14 (2/0) 17 (2/0) pea - 18 (1/2) -- 25 (2/2) 28 (2/2) 25 (2/2) 28 (2/2) 25 (2/2) 28 (2/2) movem m ? r word 26+7n (2+n/0) 26+7n (2+n/0) - 30+7n (3+n/0) 33+7n (3+n/0) 30+7n (3+n/0) 34+7n (4+n/0) 30+7n (3+n/0) 33+7n (3+n/0) long 26+11n (2+2n/0) 26+11n (2+2n/0) - 30+11n (3+2n/0) 33+11n (3+2n/0) 30+11n (3+2n/0) 34+11n (4+2n/0) 30+11n (3+2n/0) 33+11n (3+2n/0) movem r ? m word 23+7n (2/n) - 23+7n (2/n) 27+7n (3/n) 30+7n (3/n) 27+7n (3/n) 31+7n (4/n) -- long 23+11n (2/2n) - 23+11n (2/2n) 27+11n (3/2n) 30+11n (3/2n) 27+11n (3/2n) 31+11n (4/2n) -- instruction size op dn, an op m, m addx byte, word 7 (1/0) 28 (3/1) long 7 (1/0) 40 (5/2) cmpm byte, word - 18 (3/0) long - 26 (5/0) subx byte, word 7 (1/0) 28 (3/1) long 7 (1/0) 40 (5/2) abcd byte 10 (1/0) 31 (3/1) sbcd byte 10 (1/0) 31 (3/1)
1996 dec 11 85 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) table 109 miscellaneous clock periods note 1. add effective address calculation time. instruction size register memory register to memory memory to register andi to ccr - 14 (2/0) --- andi to sr - 14 (2/0) --- eori to ccr - 14 (2/0) --- eori to sr - 14 (2/0) --- exg - 13 (2/0) --- ext word 7 (1/0) --- long 7 (1/0) --- link - 25 (2/2) --- move from sr - 7 (1/0) 11 (1/1) (1) -- move to ccr - 10 (1/0) 10 (1/0) (1) -- move to sr - 10 (1/0) 10 (1/0) (1) -- move from usp - 7 (1/0) --- move to usp - 7 (1/0) --- movep word -- 25 (2/2) 22 (4/0) long -- 39 (2/4) 36 (6/0) nop - 7 (1/0) --- ori to ccr - 14 (2/0) --- ori to sr - 14 (2/0) --- reset - 154 (1/0) --- rte short format - ---- rte long format - no rerun - 140 (18/0) --- with rerun - 146 (18/0) --- return of tas - 151 (19/0) --- rtr - 22 (4/0) --- rts - 15 (3/0) --- stop - 17 (2/0) --- swap - 7 (1/0) --- unlk - 15 (3/0) ---
1996 dec 11 86 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) table 110 exception processing clock periods notes 1. the interrupt acknowledge bus cycle is assumed to take four external clock periods. 2. add effective address calculation time. 3. indicates the maximum time from when reset and halt are first sampled as negated to first instruction fetch. exception number of clock periods address error 158 (3/17) bus error 158 (3/17) interrupt 65 (4/4) (1) illegal instruction 55 (3/4) privilege instruction 55 (3/4) trace 55 (3/4) trap 52 (3/4) divide by zero 64 (3/4) (2) reset (3) 43 (4/0)
1996 dec 11 87 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 28 package outline unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 1.6 0.16 0.04 1.5 1.3 0.25 0.25 0.13 0.18 0.12 12.1 11.9 0.5 14.15 13.85 0.70 0.58 1.45 1.05 4 0 o o 0.15 0.1 0.2 1.0 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.7 0.3 sot315-1 92-03-24 95-12-19 d (1) (1) (1) 12.1 11.9 h d 14.15 13.85 e z 1.45 1.05 d b p e q e a 1 a l p q detail x l (a ) 3 b 20 c d h b p e h a 2 v m b d z d a z e e v m a x 1 80 61 60 41 40 21 y pin 1 index w m w m 0 5 10 mm scale lqfp80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm sot315-1
1996 dec 11 88 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 29 soldering 29.1 introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). 29.2 re?ow soldering reflow soldering techniques are suitable for all lqfp packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. 29.3 wave soldering wave soldering is not recommended for lqfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. even with these conditions, do not consider wave soldering lqfp packages lqfp48 (sot313-2), lqfp64 (sot314-2) or lqfp80 (sot315-1). during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 29.4 repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1996 dec 11 89 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) 30 definitions 31 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 32 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1996 dec 11 90 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) notes
1996 dec 11 91 philips semiconductors preliminary speci?cation low voltage 16-bit microcontroller P90CL301bfh (c100) notes
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1996 sca52 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 247 9145, fax. +7 095 247 9144 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - 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